2 * Copyright (C) 2015 Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __LS1043A_COMMON_H
8 #define __LS1043A_COMMON_H
11 #ifdef CONFIG_SPL_BUILD
22 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT))
25 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT))
29 #define CONFIG_REMAKE_ELF
30 #define CONFIG_FSL_LAYERSCAPE
31 #define CONFIG_LS1043A
35 #include <asm/arch/stream_id_lsch2.h>
36 #include <asm/arch/config.h>
38 /* Link Definitions */
39 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
41 #define CONFIG_SUPPORT_RAW_INITRD
43 #define CONFIG_SKIP_LOWLEVEL_INIT
45 #define CONFIG_VERY_BIG_RAM
46 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
47 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
48 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
49 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
51 #define CPU_RELEASE_ADDR secondary_boot_func
53 /* Generic Timer Definitions */
54 #define COUNTER_FREQUENCY 25000000 /* 25MHz */
56 /* Size of malloc() pool */
57 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
60 #define CONFIG_CONS_INDEX 1
61 #define CONFIG_SYS_NS16550_SERIAL
62 #define CONFIG_SYS_NS16550_REG_SIZE 1
63 #define CONFIG_SYS_NS16550_CLK (get_serial_clock())
65 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
69 #define CONFIG_SPL_FRAMEWORK
70 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
71 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
73 #define CONFIG_SPL_TEXT_BASE 0x10000000
74 #define CONFIG_SPL_MAX_SIZE 0x17000
75 #define CONFIG_SPL_STACK 0x1001e000
76 #define CONFIG_SPL_PAD_TO 0x1d000
78 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
79 CONFIG_SYS_MONITOR_LEN)
80 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
81 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
82 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
84 #ifdef CONFIG_SECURE_BOOT
85 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
87 * HDR would be appended at end of image and copied to DDR along
88 * with U-Boot image. Here u-boot max. size is 512K. So if binary
89 * size increases then increase this size in case of secure boot as
90 * it uses raw u-boot image instead of fit image.
92 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
94 #define CONFIG_SYS_MONITOR_LEN 0x100000
95 #endif /* ifdef CONFIG_SECURE_BOOT */
99 #ifdef CONFIG_NAND_BOOT
100 #define CONFIG_SPL_PBL_PAD
101 #define CONFIG_SPL_FRAMEWORK
102 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
103 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
104 #define CONFIG_SPL_TEXT_BASE 0x10000000
105 #define CONFIG_SPL_MAX_SIZE 0x1a000
106 #define CONFIG_SPL_STACK 0x1001d000
107 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
108 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
109 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000
110 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
111 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
112 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
113 #define CONFIG_SYS_MONITOR_LEN 0xa0000
118 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
119 #define CONFIG_FSL_IFC
121 * CONFIG_SYS_FLASH_BASE has the final address (core view)
122 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
123 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
124 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
126 #define CONFIG_SYS_FLASH_BASE 0x60000000
127 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
128 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
130 #ifdef CONFIG_MTD_NOR_FLASH
131 #define CONFIG_FLASH_CFI_DRIVER
132 #define CONFIG_SYS_FLASH_CFI
133 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
134 #define CONFIG_SYS_FLASH_QUIET_TEST
135 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
141 #define CONFIG_SYS_I2C
142 #define CONFIG_SYS_I2C_MXC
143 #define CONFIG_SYS_I2C_MXC_I2C1
144 #define CONFIG_SYS_I2C_MXC_I2C2
145 #define CONFIG_SYS_I2C_MXC_I2C3
146 #define CONFIG_SYS_I2C_MXC_I2C4
150 #define CONFIG_PCIE1 /* PCIE controller 1 */
151 #define CONFIG_PCIE2 /* PCIE controller 2 */
152 #define CONFIG_PCIE3 /* PCIE controller 3 */
155 #define CONFIG_NET_MULTI
156 #define CONFIG_PCI_SCAN_SHOW
157 #define CONFIG_CMD_PCI
161 /* Command line configuration */
163 #define CONFIG_CMD_ENV
169 #define CONFIG_FSL_ESDHC
170 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
176 #define CONFIG_FSL_DSPI
177 #ifdef CONFIG_FSL_DSPI
178 #define CONFIG_DM_SPI_FLASH
179 #define CONFIG_SPI_FLASH_STMICRO /* cs0 */
180 #define CONFIG_SPI_FLASH_SST /* cs1 */
181 #define CONFIG_SPI_FLASH_EON /* cs2 */
182 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
183 #define CONFIG_SF_DEFAULT_BUS 1
184 #define CONFIG_SF_DEFAULT_CS 0
191 #define CONFIG_SYS_DPAA_FMAN
192 #ifdef CONFIG_SYS_DPAA_FMAN
193 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
195 #ifdef CONFIG_NAND_BOOT
196 /* Store Fman ucode at offeset 0x160000(11 blocks). */
197 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
198 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
199 #elif defined(CONFIG_SD_BOOT)
201 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
202 * about 1MB (2040 blocks), Env is stored after the image, and the env size is
203 * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 2080(0x820).
205 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
206 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
207 #elif defined(CONFIG_QSPI_BOOT)
208 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
209 #define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000
210 #define CONFIG_ENV_SPI_BUS 0
211 #define CONFIG_ENV_SPI_CS 0
212 #define CONFIG_ENV_SPI_MAX_HZ 1000000
213 #define CONFIG_ENV_SPI_MODE 0x03
215 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
216 /* FMan fireware Pre-load address */
217 #define CONFIG_SYS_FMAN_FW_ADDR 0x60300000
219 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
220 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
224 /* Miscellaneous configurable options */
225 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
227 #define CONFIG_HWCONFIG
228 #define HWCONFIG_BUFFER_SIZE 128
231 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
232 #define MTDPARTS_DEFAULT "mtdparts=spi0.0:1m(uboot)," \
233 "5m(kernel),1m(dtb),9m(file_system)"
235 #define MTDPARTS_DEFAULT "mtdparts=60000000.nor:" \
236 "2m@0x100000(nor_bank0_uboot),"\
237 "40m@0x1100000(nor_bank0_fit)," \
238 "7m(nor_bank0_user)," \
239 "2m@0x4100000(nor_bank4_uboot)," \
240 "40m@0x5100000(nor_bank4_fit),"\
241 "-(nor_bank4_user);" \
243 "1m(nand_uboot),1m(nand_uboot_env)," \
244 "20m(nand_fit);spi0.0:1m(uboot)," \
245 "5m(kernel),1m(dtb),9m(file_system)"
248 /* Initial environment variables */
249 #define CONFIG_EXTRA_ENV_SETTINGS \
250 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
251 "loadaddr=0x80100000\0" \
252 "fdt_high=0xffffffffffffffff\0" \
253 "initrd_high=0xffffffffffffffff\0" \
254 "kernel_start=0x61100000\0" \
255 "kernel_load=0xa0000000\0" \
256 "kernel_size=0x2800000\0" \
257 "console=ttyS0,115200\0" \
258 "mtdparts=" MTDPARTS_DEFAULT "\0"
260 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
261 "earlycon=uart8250,mmio,0x21c0500 " \
264 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
265 #define CONFIG_BOOTCOMMAND "sf probe && sf read $kernel_load " \
266 "e0000 f00000 && bootm $kernel_load"
268 #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \
269 "$kernel_size && bootm $kernel_load"
273 /* Monitor Command Prompt */
274 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
275 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
276 sizeof(CONFIG_SYS_PROMPT) + 16)
277 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
278 #define CONFIG_SYS_LONGHELP
281 #define CONFIG_CMDLINE_EDITING 1
284 #define CONFIG_AUTO_COMPLETE
285 #define CONFIG_SYS_MAXARGS 64 /* max command args */
287 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
289 /* Hash command with SHA acceleration supported in hardware */
290 #ifdef CONFIG_FSL_CAAM
291 #define CONFIG_CMD_HASH
292 #define CONFIG_SHA_HW_ACCEL
295 #endif /* __LS1043A_COMMON_H */