2 * Copyright (C) 2015 Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __LS1043A_COMMON_H
8 #define __LS1043A_COMMON_H
10 #define CONFIG_REMAKE_ELF
11 #define CONFIG_FSL_LAYERSCAPE
12 #define CONFIG_LS1043A
14 #define CONFIG_SYS_FSL_CLK
17 #include <asm/arch/config.h>
19 /* Link Definitions */
20 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
22 #define CONFIG_SUPPORT_RAW_INITRD
24 #define CONFIG_SKIP_LOWLEVEL_INIT
25 #define CONFIG_BOARD_EARLY_INIT_F 1
27 #define CONFIG_VERY_BIG_RAM
28 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
29 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
30 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
31 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
33 #define CPU_RELEASE_ADDR secondary_boot_func
35 /* Generic Timer Definitions */
36 #define COUNTER_FREQUENCY 25000000 /* 25MHz */
38 /* Size of malloc() pool */
39 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
42 #define CONFIG_CONS_INDEX 1
43 #define CONFIG_SYS_NS16550_SERIAL
44 #define CONFIG_SYS_NS16550_REG_SIZE 1
45 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
47 #define CONFIG_BAUDRATE 115200
48 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
52 #define CONFIG_SPL_FRAMEWORK
53 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
54 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
55 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x500
57 #define CONFIG_SPL_TEXT_BASE 0x10000000
58 #define CONFIG_SPL_MAX_SIZE 0x1d000
59 #define CONFIG_SPL_STACK 0x1001e000
60 #define CONFIG_SPL_PAD_TO 0x1d000
62 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
63 CONFIG_SYS_MONITOR_LEN)
64 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
65 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
66 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
67 #define CONFIG_SYS_MONITOR_LEN 0xa0000
71 #ifdef CONFIG_NAND_BOOT
72 #define CONFIG_SPL_PBL_PAD
73 #define CONFIG_SPL_FRAMEWORK
74 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
75 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
76 #define CONFIG_SPL_TEXT_BASE 0x10000000
77 #define CONFIG_SPL_MAX_SIZE 0x1a000
78 #define CONFIG_SPL_STACK 0x1001d000
79 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
80 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
81 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000
82 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
83 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
84 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
85 #define CONFIG_SYS_MONITOR_LEN 0xa0000
89 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
90 #define CONFIG_FSL_IFC
92 * CONFIG_SYS_FLASH_BASE has the final address (core view)
93 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
94 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
95 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
97 #define CONFIG_SYS_FLASH_BASE 0x60000000
98 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
99 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
101 #ifndef CONFIG_SYS_NO_FLASH
102 #define CONFIG_FLASH_CFI_DRIVER
103 #define CONFIG_SYS_FLASH_CFI
104 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
105 #define CONFIG_SYS_FLASH_QUIET_TEST
106 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
111 #define CONFIG_SYS_I2C
112 #define CONFIG_SYS_I2C_MXC
113 #define CONFIG_SYS_I2C_MXC_I2C1
114 #define CONFIG_SYS_I2C_MXC_I2C2
115 #define CONFIG_SYS_I2C_MXC_I2C3
116 #define CONFIG_SYS_I2C_MXC_I2C4
119 #define CONFIG_PCIE1 /* PCIE controller 1 */
120 #define CONFIG_PCIE2 /* PCIE controller 2 */
121 #define CONFIG_PCIE3 /* PCIE controller 3 */
122 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
123 #define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
125 #define CONFIG_SYS_PCI_64BIT
127 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
128 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
129 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
130 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
132 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000
133 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
134 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
136 #define CONFIG_SYS_PCIE_MEM_BUS 0x40000000
137 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x40000000
138 #define CONFIG_SYS_PCIE_MEM_SIZE 0x40000000 /* 1G */
141 #define CONFIG_NET_MULTI
143 #define CONFIG_PCI_SCAN_SHOW
144 #define CONFIG_CMD_PCI
147 /* Command line configuration */
148 #define CONFIG_CMD_ENV
150 #define CONFIG_CMD_PXE
155 #define CONFIG_FSL_ESDHC
156 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
157 #define CONFIG_GENERIC_MMC
158 #define CONFIG_DOS_PARTITION
162 #define CONFIG_FSL_DSPI
163 #ifdef CONFIG_FSL_DSPI
164 #define CONFIG_DM_SPI_FLASH
165 #define CONFIG_SPI_FLASH_STMICRO /* cs0 */
166 #define CONFIG_SPI_FLASH_SST /* cs1 */
167 #define CONFIG_SPI_FLASH_EON /* cs2 */
168 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
169 #define CONFIG_SF_DEFAULT_BUS 1
170 #define CONFIG_SF_DEFAULT_CS 0
174 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
177 #define CONFIG_SYS_DPAA_FMAN
178 #ifdef CONFIG_SYS_DPAA_FMAN
179 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
181 #ifdef CONFIG_NAND_BOOT
182 /* Store Fman ucode at offeset 0x160000(11 blocks). */
183 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
184 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
185 #elif defined(CONFIG_SD_BOOT)
187 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
188 * about 1MB (2040 blocks), Env is stored after the image, and the env size is
189 * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 2080(0x820).
191 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
192 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
193 #elif defined(CONFIG_QSPI_BOOT)
194 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
195 #define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000
196 #define CONFIG_ENV_SPI_BUS 0
197 #define CONFIG_ENV_SPI_CS 0
198 #define CONFIG_ENV_SPI_MAX_HZ 1000000
199 #define CONFIG_ENV_SPI_MODE 0x03
201 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
202 /* FMan fireware Pre-load address */
203 #define CONFIG_SYS_FMAN_FW_ADDR 0x60300000
205 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
206 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
209 /* Miscellaneous configurable options */
210 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
211 #define CONFIG_ARCH_EARLY_INIT_R
212 #define CONFIG_BOARD_LATE_INIT
214 #define CONFIG_HWCONFIG
215 #define HWCONFIG_BUFFER_SIZE 128
217 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
218 #define MTDPARTS_DEFAULT "mtdparts=spi0.0:1m(uboot)," \
219 "5m(kernel),1m(dtb),9m(file_system)"
221 #define MTDPARTS_DEFAULT "mtdparts=60000000.nor:1m(nor_bank0_rcw)," \
222 "1m(nor_bank0_uboot),1m(nor_bank0_uboot_env)," \
223 "1m(nor_bank0_fman_uconde),40m(nor_bank0_fit)," \
224 "1m(nor_bank4_rcw),1m(nor_bank4_uboot)," \
225 "1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode)," \
226 "40m(nor_bank4_fit);7e800000.flash:" \
227 "1m(nand_uboot),1m(nand_uboot_env)," \
228 "20m(nand_fit);spi0.0:1m(uboot)," \
229 "5m(kernel),1m(dtb),9m(file_system)"
232 /* Initial environment variables */
233 #define CONFIG_EXTRA_ENV_SETTINGS \
234 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
235 "loadaddr=0x80100000\0" \
236 "fdt_high=0xffffffffffffffff\0" \
237 "initrd_high=0xffffffffffffffff\0" \
238 "kernel_start=0x61100000\0" \
239 "kernel_load=0xa0000000\0" \
240 "kernel_size=0x2800000\0" \
241 "console=ttyS0,115200\0" \
242 "mtdparts=" MTDPARTS_DEFAULT "\0"
244 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
245 "earlycon=uart8250,mmio,0x21c0500 " \
248 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
249 #define CONFIG_BOOTCOMMAND "sf probe && sf read $kernel_load " \
250 "e0000 f00000 && bootm $kernel_load"
252 #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \
253 "$kernel_size && bootm $kernel_load"
256 /* Monitor Command Prompt */
257 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
258 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
259 sizeof(CONFIG_SYS_PROMPT) + 16)
260 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
261 #define CONFIG_SYS_LONGHELP
262 #define CONFIG_CMDLINE_EDITING 1
263 #define CONFIG_AUTO_COMPLETE
264 #define CONFIG_SYS_MAXARGS 64 /* max command args */
266 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
268 /* Hash command with SHA acceleration supported in hardware */
269 #ifdef CONFIG_FSL_CAAM
270 #define CONFIG_CMD_HASH
271 #define CONFIG_SHA_HW_ACCEL
274 #endif /* __LS1043A_COMMON_H */