1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014 Freescale Semiconductor, Inc.
9 #define CONFIG_ARMV7_PSCI_1_0
11 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
13 #define CONFIG_SYS_FSL_CLK
15 #define CONFIG_SKIP_LOWLEVEL_INIT
16 #define CONFIG_DEEP_SLEEP
19 * Size of malloc() pool
21 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
23 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
24 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
26 #define CONFIG_SYS_CLK_FREQ 100000000
27 #define CONFIG_DDR_CLK_FREQ 100000000
29 #define DDR_SDRAM_CFG 0x470c0008
30 #define DDR_CS0_BNDS 0x008000bf
31 #define DDR_CS0_CONFIG 0x80014302
32 #define DDR_TIMING_CFG_0 0x50550004
33 #define DDR_TIMING_CFG_1 0xbcb38c56
34 #define DDR_TIMING_CFG_2 0x0040d120
35 #define DDR_TIMING_CFG_3 0x010e1000
36 #define DDR_TIMING_CFG_4 0x00000001
37 #define DDR_TIMING_CFG_5 0x03401400
38 #define DDR_SDRAM_CFG_2 0x00401010
39 #define DDR_SDRAM_MODE 0x00061c60
40 #define DDR_SDRAM_MODE_2 0x00180000
41 #define DDR_SDRAM_INTERVAL 0x18600618
42 #define DDR_DDR_WRLVL_CNTL 0x8655f605
43 #define DDR_DDR_WRLVL_CNTL_2 0x05060607
44 #define DDR_DDR_WRLVL_CNTL_3 0x05050505
45 #define DDR_DDR_CDR1 0x80040000
46 #define DDR_DDR_CDR2 0x00000001
47 #define DDR_SDRAM_CLK_CNTL 0x02000000
48 #define DDR_DDR_ZQ_CNTL 0x89080600
49 #define DDR_CS0_CONFIG_2 0
50 #define DDR_SDRAM_CFG_MEM_EN 0x80000000
51 #define SDRAM_CFG2_D_INIT 0x00000010
52 #define DDR_CDR2_VREF_TRAIN_EN 0x00000080
53 #define SDRAM_CFG2_FRC_SR 0x80000000
54 #define SDRAM_CFG_BI 0x00000001
56 #ifdef CONFIG_RAMBOOT_PBL
57 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg
61 #ifdef CONFIG_SD_BOOT_QSPI
62 #define CONFIG_SYS_FSL_PBL_RCW \
63 board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
65 #define CONFIG_SYS_FSL_PBL_RCW \
66 board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
69 #ifdef CONFIG_SECURE_BOOT
71 * HDR would be appended at end of image and copied to DDR along
74 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
75 #endif /* ifdef CONFIG_SECURE_BOOT */
77 #define CONFIG_SPL_TEXT_BASE 0x10000000
78 #define CONFIG_SPL_MAX_SIZE 0x1a000
79 #define CONFIG_SPL_STACK 0x1001d000
80 #define CONFIG_SPL_PAD_TO 0x1c000
82 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
83 CONFIG_SYS_MONITOR_LEN)
84 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
85 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
86 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
88 #ifdef CONFIG_U_BOOT_HDR_SIZE
90 * HDR would be appended at end of image and copied to DDR along
91 * with U-Boot image. Here u-boot max. size is 512K. So if binary
92 * size increases then increase this size in case of secure boot as
93 * it uses raw u-boot image instead of fit image.
95 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
97 #define CONFIG_SYS_MONITOR_LEN 0x100000
98 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
101 #define PHYS_SDRAM 0x80000000
102 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
104 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
105 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
107 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
108 !defined(CONFIG_QSPI_BOOT)
109 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
115 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
116 #define CONFIG_FSL_IFC
117 #define CONFIG_SYS_FLASH_BASE 0x60000000
118 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
120 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
121 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
122 CSPR_PORT_SIZE_16 | \
125 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
127 /* NOR Flash Timing Params */
128 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
130 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
131 FTIM0_NOR_TEADC(0x5) | \
132 FTIM0_NOR_TAVDS(0x0) | \
133 FTIM0_NOR_TEAHC(0x5))
134 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
135 FTIM1_NOR_TRAD_NOR(0x1A) | \
136 FTIM1_NOR_TSEQRAD_NOR(0x13))
137 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
138 FTIM2_NOR_TCH(0x4) | \
139 FTIM2_NOR_TWP(0x1c) | \
140 FTIM2_NOR_TWPH(0x0e))
141 #define CONFIG_SYS_NOR_FTIM3 0
143 #define CONFIG_SYS_FLASH_QUIET_TEST
144 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
146 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
147 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
148 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
149 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
151 #define CONFIG_SYS_FLASH_EMPTY_INFO
152 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
154 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
155 #define CONFIG_SYS_WRITE_SWAPPED_DATA
160 #define CONFIG_SYS_CPLD_BASE 0x7fb00000
161 #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
163 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
164 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
168 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
169 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
170 CSOR_NOR_NOR_MODE_AVD_NOR | \
173 /* CPLD Timing parameters for IFC GPCM */
174 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
175 FTIM0_GPCM_TEADC(0xf) | \
176 FTIM0_GPCM_TEAHC(0xf))
177 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
178 FTIM1_GPCM_TRAD(0x3f))
179 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
180 FTIM2_GPCM_TCH(0xf) | \
181 FTIM2_GPCM_TWP(0xff))
182 #define CONFIG_SYS_FPGA_FTIM3 0x0
183 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
184 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
185 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
186 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
187 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
188 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
189 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
190 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
191 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT
192 #define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR
193 #define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK
194 #define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR
195 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0
196 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1
197 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2
198 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3
204 #define CONFIG_LPUART_32B_REG
206 #define CONFIG_SYS_NS16550_SERIAL
207 #ifndef CONFIG_DM_SERIAL
208 #define CONFIG_SYS_NS16550_REG_SIZE 1
210 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
216 #define CONFIG_SYS_I2C
217 #define CONFIG_SYS_I2C_MXC
218 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
219 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
220 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
223 #define CONFIG_ID_EEPROM
224 #define CONFIG_SYS_I2C_EEPROM_NXID
225 #define CONFIG_SYS_EEPROM_BUS_NUM 1
226 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
227 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
228 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
229 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
236 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
238 #define QSPI0_AMBA_BASE 0x40000000
239 #define FSL_QSPI_FLASH_SIZE (1 << 24)
240 #define FSL_QSPI_FLASH_NUM 2
246 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
247 #define CONFIG_DM_SPI_FLASH
253 #ifdef CONFIG_VIDEO_FSL_DCU_FB
254 #define CONFIG_VIDEO_LOGO
255 #define CONFIG_VIDEO_BMP_LOGO
257 #define CONFIG_FSL_DCU_SII9022A
258 #define CONFIG_SYS_I2C_DVI_BUS_NUM 1
259 #define CONFIG_SYS_I2C_DVI_ADDR 0x39
266 #ifdef CONFIG_TSEC_ENET
267 #define CONFIG_MII_DEFAULT_TSEC 1
268 #define CONFIG_TSEC1 1
269 #define CONFIG_TSEC1_NAME "eTSEC1"
270 #define CONFIG_TSEC2 1
271 #define CONFIG_TSEC2_NAME "eTSEC2"
272 #define CONFIG_TSEC3 1
273 #define CONFIG_TSEC3_NAME "eTSEC3"
275 #define TSEC1_PHY_ADDR 2
276 #define TSEC2_PHY_ADDR 0
277 #define TSEC3_PHY_ADDR 1
279 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
280 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
281 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
283 #define TSEC1_PHYIDX 0
284 #define TSEC2_PHYIDX 0
285 #define TSEC3_PHYIDX 0
287 #define CONFIG_ETHPRIME "eTSEC1"
289 #define CONFIG_PHY_ATHEROS
291 #define CONFIG_HAS_ETH0
292 #define CONFIG_HAS_ETH1
293 #define CONFIG_HAS_ETH2
297 #define CONFIG_PCIE1 /* PCIE controller 1 */
298 #define CONFIG_PCIE2 /* PCIE controller 2 */
301 #define CONFIG_PCI_SCAN_SHOW
304 #define CONFIG_CMDLINE_TAG
306 #define CONFIG_PEN_ADDR_BIG_ENDIAN
307 #define CONFIG_LAYERSCAPE_NS_ACCESS
308 #define CONFIG_SMP_PEN_ADDR 0x01ee0200
309 #define COUNTER_FREQUENCY 12500000
311 #define CONFIG_HWCONFIG
312 #define HWCONFIG_BUFFER_SIZE 256
314 #define CONFIG_FSL_DEVICE_DISABLE
316 #define BOOT_TARGET_DEVICES(func) \
320 #include <config_distro_bootcmd.h>
323 #define CONFIG_EXTRA_ENV_SETTINGS \
324 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
325 "initrd_high=0xffffffff\0" \
326 "fdt_high=0xffffffff\0" \
327 "fdt_addr=0x64f00000\0" \
328 "kernel_addr=0x65000000\0" \
329 "scriptaddr=0x80000000\0" \
330 "scripthdraddr=0x80080000\0" \
331 "fdtheader_addr_r=0x80100000\0" \
332 "kernelheader_addr_r=0x80200000\0" \
333 "kernel_addr_r=0x81000000\0" \
334 "fdt_addr_r=0x90000000\0" \
335 "ramdisk_addr_r=0xa0000000\0" \
336 "load_addr=0xa0000000\0" \
337 "kernel_size=0x2800000\0" \
338 "kernel_addr_sd=0x8000\0" \
339 "kernel_size_sd=0x14000\0" \
341 "boot_scripts=ls1021atwr_boot.scr\0" \
342 "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \
343 "scan_dev_for_boot_part=" \
344 "part list ${devtype} ${devnum} devplist; " \
345 "env exists devplist || setenv devplist 1; " \
346 "for distro_bootpart in ${devplist}; do " \
347 "if fstype ${devtype} " \
348 "${devnum}:${distro_bootpart} " \
349 "bootfstype; then " \
350 "run scan_dev_for_boot; " \
353 "scan_dev_for_boot=" \
354 "echo Scanning ${devtype} " \
355 "${devnum}:${distro_bootpart}...; " \
356 "for prefix in ${boot_prefixes}; do " \
357 "run scan_dev_for_scripts; " \
361 "load ${devtype} ${devnum}:${distro_bootpart} " \
362 "${scriptaddr} ${prefix}${script}; " \
363 "env exists secureboot && load ${devtype} " \
364 "${devnum}:${distro_bootpart} " \
365 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
366 "&& esbc_validate ${scripthdraddr};" \
367 "source ${scriptaddr}\0" \
368 "installer=load mmc 0:2 $load_addr " \
369 "/flex_installer_arm32.itb; " \
370 "bootm $load_addr#ls1021atwr\0" \
371 "qspi_bootcmd=echo Trying load from qspi..;" \
372 "sf probe && sf read $load_addr " \
373 "$kernel_addr $kernel_size && bootm $load_addr#$board\0" \
374 "nor_bootcmd=echo Trying load from nor..;" \
375 "cp.b $kernel_addr $load_addr " \
376 "$kernel_size && bootm $load_addr#$board\0"
378 #define CONFIG_EXTRA_ENV_SETTINGS \
379 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
380 "initrd_high=0xffffffff\0" \
381 "fdt_high=0xffffffff\0" \
382 "fdt_addr=0x64f00000\0" \
383 "kernel_addr=0x61000000\0" \
384 "kernelheader_addr=0x60800000\0" \
385 "scriptaddr=0x80000000\0" \
386 "scripthdraddr=0x80080000\0" \
387 "fdtheader_addr_r=0x80100000\0" \
388 "kernelheader_addr_r=0x80200000\0" \
389 "kernel_addr_r=0x81000000\0" \
390 "kernelheader_size=0x40000\0" \
391 "fdt_addr_r=0x90000000\0" \
392 "ramdisk_addr_r=0xa0000000\0" \
393 "load_addr=0xa0000000\0" \
394 "kernel_size=0x2800000\0" \
395 "kernel_addr_sd=0x8000\0" \
396 "kernel_size_sd=0x14000\0" \
397 "kernelhdr_addr_sd=0x4000\0" \
398 "kernelhdr_size_sd=0x10\0" \
400 "boot_scripts=ls1021atwr_boot.scr\0" \
401 "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \
402 "scan_dev_for_boot_part=" \
403 "part list ${devtype} ${devnum} devplist; " \
404 "env exists devplist || setenv devplist 1; " \
405 "for distro_bootpart in ${devplist}; do " \
406 "if fstype ${devtype} " \
407 "${devnum}:${distro_bootpart} " \
408 "bootfstype; then " \
409 "run scan_dev_for_boot; " \
412 "scan_dev_for_boot=" \
413 "echo Scanning ${devtype} " \
414 "${devnum}:${distro_bootpart}...; " \
415 "for prefix in ${boot_prefixes}; do " \
416 "run scan_dev_for_scripts; " \
420 "load ${devtype} ${devnum}:${distro_bootpart} " \
421 "${scriptaddr} ${prefix}${script}; " \
422 "env exists secureboot && load ${devtype} " \
423 "${devnum}:${distro_bootpart} " \
424 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
425 "&& esbc_validate ${scripthdraddr};" \
426 "source ${scriptaddr}\0" \
427 "qspi_bootcmd=echo Trying load from qspi..;" \
428 "sf probe && sf read $load_addr " \
429 "$kernel_addr $kernel_size; env exists secureboot " \
430 "&& sf read $kernelheader_addr_r $kernelheader_addr " \
431 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
432 "bootm $load_addr#$board\0" \
433 "nor_bootcmd=echo Trying load from nor..;" \
434 "cp.b $kernel_addr $load_addr " \
435 "$kernel_size; env exists secureboot " \
436 "&& cp.b $kernelheader_addr $kernelheader_addr_r " \
437 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
438 "bootm $load_addr#$board\0" \
439 "sd_bootcmd=echo Trying load from SD ..;" \
440 "mmcinfo && mmc read $load_addr " \
441 "$kernel_addr_sd $kernel_size_sd && " \
442 "env exists secureboot && mmc read $kernelheader_addr_r " \
443 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
444 " && esbc_validate ${kernelheader_addr_r};" \
445 "bootm $load_addr#$board\0"
448 #undef CONFIG_BOOTCOMMAND
449 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
450 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd" \
451 "env exists secureboot && esbc_halt"
452 #elif defined(CONFIG_SD_BOOT)
453 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
454 "env exists secureboot && esbc_halt;"
456 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd;" \
457 "env exists secureboot && esbc_halt;"
461 * Miscellaneous configurable options
464 #define CONFIG_SYS_MEMTEST_START 0x80000000
465 #define CONFIG_SYS_MEMTEST_END 0x9fffffff
467 #define CONFIG_SYS_LOAD_ADDR 0x82000000
469 #define CONFIG_LS102XA_STREAM_ID
471 #define CONFIG_SYS_INIT_SP_OFFSET \
472 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
473 #define CONFIG_SYS_INIT_SP_ADDR \
474 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
476 #ifdef CONFIG_SPL_BUILD
477 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
479 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
482 #define CONFIG_SYS_QE_FW_ADDR 0x60940000
487 #define CONFIG_ENV_OVERWRITE
489 #if defined(CONFIG_SD_BOOT)
490 #define CONFIG_ENV_OFFSET 0x300000
491 #define CONFIG_SYS_MMC_ENV_DEV 0
492 #define CONFIG_ENV_SIZE 0x20000
493 #elif defined(CONFIG_QSPI_BOOT)
494 #define CONFIG_ENV_SIZE 0x2000
495 #define CONFIG_ENV_OFFSET 0x300000
496 #define CONFIG_ENV_SECT_SIZE 0x10000
498 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
499 #define CONFIG_ENV_SIZE 0x20000
500 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
503 #include <asm/fsl_secure_boot.h>
504 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */