2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <config_cmd_default.h>
12 #define CONFIG_LS102XA
14 #define CONFIG_SYS_GENERIC_BOARD
16 #define CONFIG_DISPLAY_CPUINFO
17 #define CONFIG_DISPLAY_BOARDINFO
19 #define CONFIG_SKIP_LOWLEVEL_INIT
20 #define CONFIG_BOARD_EARLY_INIT_F
23 * Size of malloc() pool
25 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
27 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
28 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
31 * Generic Timer Definitions
33 #define GENERIC_TIMER_CLK 12500000
35 #define CONFIG_SYS_CLK_FREQ 100000000
36 #define CONFIG_DDR_CLK_FREQ 100000000
38 #ifndef CONFIG_SYS_TEXT_BASE
39 #define CONFIG_SYS_TEXT_BASE 0x67f80000
42 #define CONFIG_NR_DRAM_BANKS 1
43 #define PHYS_SDRAM 0x80000000
44 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
46 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
47 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
49 #define CONFIG_SYS_HAS_SERDES
51 #define CONFIG_FSL_CAAM /* Enable CAAM */
53 #if !defined(CONFIG_SDCARD) && !defined(CONFIG_NAND) && !defined(CONFIG_SPI)
60 #define CONFIG_FSL_IFC
61 #define CONFIG_SYS_FLASH_BASE 0x60000000
62 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
64 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
65 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
69 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
71 /* NOR Flash Timing Params */
72 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
74 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
75 FTIM0_NOR_TEADC(0x5) | \
76 FTIM0_NOR_TAVDS(0x0) | \
78 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
79 FTIM1_NOR_TRAD_NOR(0x1A) | \
80 FTIM1_NOR_TSEQRAD_NOR(0x13))
81 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
82 FTIM2_NOR_TCH(0x4) | \
83 FTIM2_NOR_TWP(0x1c) | \
85 #define CONFIG_SYS_NOR_FTIM3 0
87 #define CONFIG_FLASH_CFI_DRIVER
88 #define CONFIG_SYS_FLASH_CFI
89 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
90 #define CONFIG_SYS_FLASH_QUIET_TEST
91 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
93 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
94 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
95 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
96 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
98 #define CONFIG_SYS_FLASH_EMPTY_INFO
99 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
101 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
102 #define CONFIG_SYS_WRITE_SWAPPED_DATA
106 #define CONFIG_SYS_CPLD_BASE 0x7fb00000
107 #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
109 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
110 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
114 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
115 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
116 CSOR_NOR_NOR_MODE_AVD_NOR | \
119 /* CPLD Timing parameters for IFC GPCM */
120 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
121 FTIM0_GPCM_TEADC(0xf) | \
122 FTIM0_GPCM_TEAHC(0xf))
123 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
124 FTIM1_GPCM_TRAD(0x3f))
125 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
126 FTIM2_GPCM_TCH(0xf) | \
127 FTIM2_GPCM_TWP(0xff))
128 #define CONFIG_SYS_FPGA_FTIM3 0x0
129 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
130 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
131 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
132 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
133 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
134 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
135 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
136 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
137 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT
138 #define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR
139 #define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK
140 #define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR
141 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0
142 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1
143 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2
144 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3
149 #define CONFIG_CONS_INDEX 1
150 #define CONFIG_SYS_NS16550
151 #define CONFIG_SYS_NS16550_SERIAL
152 #define CONFIG_SYS_NS16550_REG_SIZE 1
153 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
155 #define CONFIG_BAUDRATE 115200
160 #define CONFIG_CMD_I2C
161 #define CONFIG_SYS_I2C
162 #define CONFIG_SYS_I2C_MXC
165 #ifndef CONFIG_SD_BOOT
166 #define CONFIG_ID_EEPROM
167 #define CONFIG_SYS_I2C_EEPROM_NXID
168 #define CONFIG_SYS_EEPROM_BUS_NUM 1
169 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
170 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
171 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
172 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
179 #define CONFIG_CMD_MMC
180 #define CONFIG_FSL_ESDHC
181 #define CONFIG_GENERIC_MMC
186 #define CONFIG_FSL_DCU_FB
188 #ifdef CONFIG_FSL_DCU_FB
190 #define CONFIG_CMD_BMP
191 #define CONFIG_CFB_CONSOLE
192 #define CONFIG_VGA_AS_SINGLE_DEVICE
193 #define CONFIG_VIDEO_LOGO
194 #define CONFIG_VIDEO_BMP_LOGO
196 #define CONFIG_FSL_DCU_SII9022A
197 #define CONFIG_SYS_I2C_DVI_BUS_NUM 1
198 #define CONFIG_SYS_I2C_DVI_ADDR 0x39
204 #define CONFIG_TSEC_ENET
206 #ifdef CONFIG_TSEC_ENET
208 #define CONFIG_MII_DEFAULT_TSEC 1
209 #define CONFIG_TSEC1 1
210 #define CONFIG_TSEC1_NAME "eTSEC1"
211 #define CONFIG_TSEC2 1
212 #define CONFIG_TSEC2_NAME "eTSEC2"
213 #define CONFIG_TSEC3 1
214 #define CONFIG_TSEC3_NAME "eTSEC3"
216 #define TSEC1_PHY_ADDR 2
217 #define TSEC2_PHY_ADDR 0
218 #define TSEC3_PHY_ADDR 1
220 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
221 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
222 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
224 #define TSEC1_PHYIDX 0
225 #define TSEC2_PHYIDX 0
226 #define TSEC3_PHYIDX 0
228 #define CONFIG_ETHPRIME "eTSEC1"
230 #define CONFIG_PHY_GIGE
231 #define CONFIG_PHYLIB
232 #define CONFIG_PHY_ATHEROS
234 #define CONFIG_HAS_ETH0
235 #define CONFIG_HAS_ETH1
236 #define CONFIG_HAS_ETH2
239 #define CONFIG_CMD_PING
240 #define CONFIG_CMD_DHCP
241 #define CONFIG_CMD_MII
242 #define CONFIG_CMD_NET
244 #define CONFIG_CMDLINE_TAG
245 #define CONFIG_CMDLINE_EDITING
246 #define CONFIG_CMD_IMLS
248 #define CONFIG_HWCONFIG
249 #define HWCONFIG_BUFFER_SIZE 128
251 #define CONFIG_BOOTDELAY 3
253 #define CONFIG_EXTRA_ENV_SETTINGS \
254 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
255 "initrd_high=0xcfffffff\0" \
256 "fdt_high=0xcfffffff\0"
259 * Miscellaneous configurable options
261 #define CONFIG_SYS_LONGHELP /* undef to save memory */
262 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
263 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
264 #define CONFIG_SYS_PROMPT "=> "
265 #define CONFIG_AUTO_COMPLETE
266 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
267 #define CONFIG_SYS_PBSIZE \
268 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
269 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
270 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
272 #define CONFIG_CMD_ENV_EXISTS
273 #define CONFIG_CMD_GREPENV
274 #define CONFIG_CMD_MEMINFO
275 #define CONFIG_CMD_MEMTEST
276 #define CONFIG_SYS_MEMTEST_START 0x80000000
277 #define CONFIG_SYS_MEMTEST_END 0x9fffffff
279 #define CONFIG_SYS_LOAD_ADDR 0x82000000
283 * The stack sizes are set up in start.S using the settings below
285 #define CONFIG_STACKSIZE (30 * 1024)
287 #define CONFIG_SYS_INIT_SP_OFFSET \
288 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
289 #define CONFIG_SYS_INIT_SP_ADDR \
290 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
292 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
294 #define CONFIG_SYS_QE_FW_ADDR 0x67f40000
299 #define CONFIG_ENV_OVERWRITE
301 #define CONFIG_ENV_IS_IN_FLASH
302 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
303 #define CONFIG_ENV_SIZE 0x20000
304 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
306 #define CONFIG_OF_LIBFDT
307 #define CONFIG_OF_BOARD_SETUP
308 #define CONFIG_CMD_BOOTZ
310 #define CONFIG_MISC_INIT_R
312 /* Hash command with SHA acceleration supported in hardware */
313 #define CONFIG_CMD_HASH
314 #define CONFIG_SHA_HW_ACCEL
316 #ifdef CONFIG_SECURE_BOOT
317 #define CONFIG_CMD_BLOB