1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014 Freescale Semiconductor, Inc.
9 #define CONFIG_ARMV7_PSCI_1_0
11 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
13 #define CONFIG_SYS_FSL_CLK
15 #define CONFIG_SKIP_LOWLEVEL_INIT
17 #define CONFIG_DEEP_SLEEP
20 * Size of malloc() pool
22 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
24 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
25 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
28 unsigned long get_board_sys_clk(void);
29 unsigned long get_board_ddr_clk(void);
32 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
33 #define CONFIG_SYS_CLK_FREQ 100000000
34 #define CONFIG_DDR_CLK_FREQ 100000000
35 #define CONFIG_QIXIS_I2C_ACCESS
37 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
38 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
41 #ifdef CONFIG_RAMBOOT_PBL
42 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg
46 #ifdef CONFIG_SD_BOOT_QSPI
47 #define CONFIG_SYS_FSL_PBL_RCW \
48 board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg
50 #define CONFIG_SYS_FSL_PBL_RCW \
51 board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg
54 #define CONFIG_SPL_MAX_SIZE 0x1a000
55 #define CONFIG_SPL_STACK 0x1001d000
56 #define CONFIG_SPL_PAD_TO 0x1c000
58 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
59 CONFIG_SYS_MONITOR_LEN)
60 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
61 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
62 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
63 #define CONFIG_SYS_MONITOR_LEN 0xc0000
66 #ifdef CONFIG_NAND_BOOT
67 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
69 #define CONFIG_SPL_MAX_SIZE 0x1a000
70 #define CONFIG_SPL_STACK 0x1001d000
71 #define CONFIG_SPL_PAD_TO 0x1c000
73 #define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10)
74 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
75 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
76 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
77 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
79 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000
80 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
81 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
82 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
83 #define CONFIG_SYS_MONITOR_LEN 0x80000
86 #define CONFIG_DDR_SPD
87 #define SPD_EEPROM_ADDRESS 0x51
88 #define CONFIG_SYS_SPD_BUS_NUM 0
90 #ifndef CONFIG_SYS_FSL_DDR4
91 #define CONFIG_SYS_DDR_RAW_TIMING
93 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
94 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
96 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
97 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
99 #define CONFIG_DDR_ECC
100 #ifdef CONFIG_DDR_ECC
101 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
102 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
105 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
106 !defined(CONFIG_QSPI_BOOT)
107 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
113 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
114 #define CONFIG_FSL_IFC
115 #define CONFIG_SYS_FLASH_BASE 0x60000000
116 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
118 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
119 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
120 CSPR_PORT_SIZE_16 | \
123 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
124 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
126 CSPR_PORT_SIZE_16 | \
129 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
131 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
133 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
134 FTIM0_NOR_TEADC(0x5) | \
135 FTIM0_NOR_TEAHC(0x5))
136 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
137 FTIM1_NOR_TRAD_NOR(0x1a) | \
138 FTIM1_NOR_TSEQRAD_NOR(0x13))
139 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
140 FTIM2_NOR_TCH(0x4) | \
141 FTIM2_NOR_TWPH(0xe) | \
143 #define CONFIG_SYS_NOR_FTIM3 0
145 #define CONFIG_SYS_FLASH_QUIET_TEST
146 #define CONFIG_FLASH_SHOW_PROGRESS 45
147 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
148 #define CONFIG_SYS_WRITE_SWAPPED_DATA
150 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
151 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
152 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
153 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
155 #define CONFIG_SYS_FLASH_EMPTY_INFO
156 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
157 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
160 * NAND Flash Definitions
162 #define CONFIG_NAND_FSL_IFC
164 #define CONFIG_SYS_NAND_BASE 0x7e800000
165 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
167 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
169 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
173 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
174 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
175 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
176 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
177 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
178 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
179 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
180 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
182 #define CONFIG_SYS_NAND_ONFI_DETECTION
184 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
185 FTIM0_NAND_TWP(0x18) | \
186 FTIM0_NAND_TWCHT(0x7) | \
188 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
189 FTIM1_NAND_TWBE(0x39) | \
190 FTIM1_NAND_TRR(0xe) | \
191 FTIM1_NAND_TRP(0x18))
192 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
193 FTIM2_NAND_TREH(0xa) | \
194 FTIM2_NAND_TWHRE(0x1e))
195 #define CONFIG_SYS_NAND_FTIM3 0x0
197 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
198 #define CONFIG_SYS_MAX_NAND_DEVICE 1
200 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
206 #define CONFIG_FSL_QIXIS
208 #ifdef CONFIG_FSL_QIXIS
209 #define QIXIS_BASE 0x7fb00000
210 #define QIXIS_BASE_PHYS QIXIS_BASE
211 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
212 #define QIXIS_LBMAP_SWITCH 6
213 #define QIXIS_LBMAP_MASK 0x0f
214 #define QIXIS_LBMAP_SHIFT 0
215 #define QIXIS_LBMAP_DFLTBANK 0x00
216 #define QIXIS_LBMAP_ALTBANK 0x04
217 #define QIXIS_PWR_CTL 0x21
218 #define QIXIS_PWR_CTL_POWEROFF 0x80
219 #define QIXIS_RST_CTL_RESET 0x44
220 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
221 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
222 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
223 #define QIXIS_CTL_SYS 0x5
224 #define QIXIS_CTL_SYS_EVTSW_MASK 0x0c
225 #define QIXIS_CTL_SYS_EVTSW_IRQ 0x04
226 #define QIXIS_RST_FORCE_3 0x45
227 #define QIXIS_RST_FORCE_3_PCIESLOT1 0x80
228 #define QIXIS_PWR_CTL2 0x21
229 #define QIXIS_PWR_CTL2_PCTL 0x2
231 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
232 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
236 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
237 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
238 CSOR_NOR_NOR_MODE_AVD_NOR | \
242 * QIXIS Timing parameters for IFC GPCM
244 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \
245 FTIM0_GPCM_TEADC(0xe) | \
246 FTIM0_GPCM_TEAHC(0xe))
247 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \
248 FTIM1_GPCM_TRAD(0x1f))
249 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \
250 FTIM2_GPCM_TCH(0xe) | \
251 FTIM2_GPCM_TWP(0xf0))
252 #define CONFIG_SYS_FPGA_FTIM3 0x0
255 #if defined(CONFIG_NAND_BOOT)
256 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
257 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
258 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
259 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
260 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
261 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
262 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
263 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
264 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
265 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
266 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
267 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
268 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
269 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
270 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
271 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
272 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
273 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
274 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
275 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
276 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
277 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
278 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
279 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
280 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
281 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
282 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
283 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
284 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
285 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
286 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
287 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
289 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
290 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
291 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
292 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
293 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
294 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
295 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
296 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
297 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
298 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
299 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
300 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
301 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
302 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
303 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
304 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
305 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
306 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
307 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
308 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
309 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
310 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
311 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
312 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
313 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
314 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
315 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
316 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
317 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
318 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
319 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
320 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
327 #define CONFIG_LPUART_32B_REG
329 #define CONFIG_SYS_NS16550_SERIAL
330 #ifndef CONFIG_DM_SERIAL
331 #define CONFIG_SYS_NS16550_REG_SIZE 1
333 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
339 #define CONFIG_SYS_I2C
340 #define CONFIG_SYS_I2C_MXC
341 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
342 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
343 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
346 #define CONFIG_ID_EEPROM
347 #define CONFIG_SYS_I2C_EEPROM_NXID
348 #define CONFIG_SYS_EEPROM_BUS_NUM 0
349 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
350 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
351 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
352 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
355 * I2C bus multiplexer
357 #define I2C_MUX_PCA_ADDR_PRI 0x77
358 #define I2C_MUX_CH_DEFAULT 0x8
359 #define I2C_MUX_CH_CH7301 0xC
366 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
368 #define QSPI0_AMBA_BASE 0x40000000
369 #define FSL_QSPI_FLASH_SIZE (1 << 24)
370 #define FSL_QSPI_FLASH_NUM 2
375 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
376 #define CONFIG_DM_SPI_FLASH
377 #define CONFIG_SPI_FLASH_DATAFLASH
384 #ifdef CONFIG_VIDEO_FSL_DCU_FB
385 #define CONFIG_VIDEO_LOGO
386 #define CONFIG_VIDEO_BMP_LOGO
388 #define CONFIG_FSL_DIU_CH7301
389 #define CONFIG_SYS_I2C_DVI_BUS_NUM 0
390 #define CONFIG_SYS_I2C_QIXIS_ADDR 0x66
391 #define CONFIG_SYS_I2C_DVI_ADDR 0x75
398 #ifdef CONFIG_TSEC_ENET
399 #define CONFIG_MII_DEFAULT_TSEC 3
400 #define CONFIG_TSEC1 1
401 #define CONFIG_TSEC1_NAME "eTSEC1"
402 #define CONFIG_TSEC2 1
403 #define CONFIG_TSEC2_NAME "eTSEC2"
404 #define CONFIG_TSEC3 1
405 #define CONFIG_TSEC3_NAME "eTSEC3"
407 #define TSEC1_PHY_ADDR 1
408 #define TSEC2_PHY_ADDR 2
409 #define TSEC3_PHY_ADDR 3
411 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
412 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
413 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
415 #define TSEC1_PHYIDX 0
416 #define TSEC2_PHYIDX 0
417 #define TSEC3_PHYIDX 0
419 #define CONFIG_ETHPRIME "eTSEC1"
421 #define CONFIG_PHY_REALTEK
423 #define CONFIG_HAS_ETH0
424 #define CONFIG_HAS_ETH1
425 #define CONFIG_HAS_ETH2
427 #define CONFIG_FSL_SGMII_RISER 1
428 #define SGMII_RISER_PHY_OFFSET 0x1b
430 #ifdef CONFIG_FSL_SGMII_RISER
431 #define CONFIG_SYS_TBIPA_VALUE 8
437 #define CONFIG_PCIE1 /* PCIE controller 1 */
438 #define CONFIG_PCIE2 /* PCIE controller 2 */
441 #define CONFIG_PCI_SCAN_SHOW
444 #define CONFIG_CMDLINE_TAG
446 #define CONFIG_PEN_ADDR_BIG_ENDIAN
447 #define CONFIG_LAYERSCAPE_NS_ACCESS
448 #define CONFIG_SMP_PEN_ADDR 0x01ee0200
449 #define COUNTER_FREQUENCY 12500000
451 #define CONFIG_HWCONFIG
452 #define HWCONFIG_BUFFER_SIZE 256
454 #define CONFIG_FSL_DEVICE_DISABLE
457 #define CONFIG_SYS_QE_FW_ADDR 0x60940000
460 #define CONFIG_EXTRA_ENV_SETTINGS \
461 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
462 "fdt_high=0xffffffff\0" \
463 "initrd_high=0xffffffff\0" \
464 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
466 #define CONFIG_EXTRA_ENV_SETTINGS \
467 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
468 "fdt_high=0xffffffff\0" \
469 "initrd_high=0xffffffff\0" \
470 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
474 * Miscellaneous configurable options
477 #define CONFIG_SYS_MEMTEST_START 0x80000000
478 #define CONFIG_SYS_MEMTEST_END 0x9fffffff
480 #define CONFIG_SYS_LOAD_ADDR 0x82000000
482 #define CONFIG_LS102XA_STREAM_ID
484 #define CONFIG_SYS_INIT_SP_OFFSET \
485 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
486 #define CONFIG_SYS_INIT_SP_ADDR \
487 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
489 #ifdef CONFIG_SPL_BUILD
490 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
492 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
498 #define CONFIG_ENV_OVERWRITE
500 #if defined(CONFIG_SD_BOOT)
501 #define CONFIG_ENV_OFFSET 0x300000
502 #define CONFIG_SYS_MMC_ENV_DEV 0
503 #define CONFIG_ENV_SIZE 0x2000
504 #elif defined(CONFIG_QSPI_BOOT)
505 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
506 #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
507 #define CONFIG_ENV_SECT_SIZE 0x10000
508 #elif defined(CONFIG_NAND_BOOT)
509 #define CONFIG_ENV_SIZE 0x2000
510 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
512 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
513 #define CONFIG_ENV_SIZE 0x2000
514 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
517 #include <asm/fsl_secure_boot.h>
518 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */