3 * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de.
5 * Configuration for the Logotronic DL board.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * include/configs/logodl.h - configuration options, board specific
34 * High Level Configuration Options
37 #define CONFIG_PXA250 1 /* This is an PXA250 CPU */
38 #define CONFIG_GEALOG 1 /* on a Logotronic GEALOG SG board */
40 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
41 /* for timer/console/ethernet */
47 * select serial console configuration
49 #define CONFIG_FFUART 1 /* we use FFUART */
51 /* allow to overwrite serial and ethaddr */
52 #define CONFIG_ENV_OVERWRITE
54 #define CONFIG_BAUDRATE 19200
55 #undef CONFIG_MISC_INIT_R /* FIXME: misc_init_r() missing */
61 #define CONFIG_BOOTP_BOOTFILESIZE
62 #define CONFIG_BOOTP_BOOTPATH
63 #define CONFIG_BOOTP_GATEWAY
64 #define CONFIG_BOOTP_HOSTNAME
68 * Command line configuration.
70 #define CONFIG_CMD_ASKENV
71 #define CONFIG_CMD_ECHO
72 #define CONFIG_CMD_SAVEENV
73 #define CONFIG_CMD_FLASH
74 #define CONFIG_CMD_MEMORY
75 #define CONFIG_CMD_RUN
78 #define CONFIG_BOOTDELAY 3
79 /* #define CONFIG_BOOTARGS "root=/dev/nfs ip=bootp console=ttyS0,19200" */
80 #define CONFIG_BOOTARGS "console=ttyS0,19200"
81 #define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF
82 #define CONFIG_NETMASK 255.255.255.0
83 #define CONFIG_IPADDR 192.168.1.56
84 #define CONFIG_SERVERIP 192.168.1.2
85 #define CONFIG_BOOTCOMMAND "bootm 0x40000"
86 #define CONFIG_SHOW_BOOT_PROGRESS
88 #define CONFIG_CMDLINE_TAG 1
91 * Miscellaneous configurable options
95 * Size of malloc() pool; this lives below the uppermost 128 KiB which are
96 * used for the RAM copy of the uboot code
99 #define CONFIG_SYS_MALLOC_LEN (256*1024)
101 #define CONFIG_SYS_LONGHELP /* undef to save memory */
102 #define CONFIG_SYS_PROMPT "uboot> " /* Monitor Command Prompt */
103 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
104 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
105 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
106 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
108 #define CONFIG_SYS_MEMTEST_START 0x08000000 /* memtest works on */
109 #define CONFIG_SYS_MEMTEST_END 0x0800ffff /* 64 KiB */
111 #define CONFIG_SYS_LOAD_ADDR 0x08000000 /* load kernel to this address */
113 #define CONFIG_SYS_HZ 1000
114 /* RS: the oscillator is actually 3680130?? */
116 #define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */
118 /* ^^^^^ Memory Speed 99.53 MHz */
119 /* ^^ Run Mode Speed = 2x Mem Speed */
120 /* ^^ Turbo Mode Sp. = 1x Run M. Sp. */
122 #define CONFIG_SYS_MONITOR_LEN 0x20000 /* 128 KiB */
124 /* valid baudrates */
125 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
128 * SMSC91C111 Network Card
131 #define CONFIG_DRIVER_SMC91111 1
132 #define CONFIG_SMC91111_BASE 0x10000000 /* chip select 4 */
133 #undef CONFIG_SMC_USE_32_BIT /* 16 bit bus access */
134 #undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */
135 #undef CONFIG_SHOW_ACTIVITY
136 #define CONFIG_NET_RETRY_COUNT 10 /* # of retries */
142 * The stack sizes are set up in start.S using the settings below
144 #define CONFIG_STACKSIZE (128*1024) /* regular stack */
145 #ifdef CONFIG_USE_IRQ
146 #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
147 #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
151 * Physical Memory Map
153 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of RAM */
154 #define PHYS_SDRAM_1 0x08000000 /* SRAM Bank #1 */
155 #define PHYS_SDRAM_1_SIZE (4*1024*1024) /* 4 MB */
157 #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
158 #define PHYS_FLASH_2 0x01000000 /* Flash Bank #2 */
159 #define PHYS_FLASH_SIZE (32*1024*1024) /* 32 MB */
161 #define CONFIG_SYS_DRAM_BASE PHYS_SDRAM_1 /* RAM starts here */
162 #define CONFIG_SYS_DRAM_SIZE PHYS_SDRAM_1_SIZE
164 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
170 * GP?? == FOOBAR is 0/1
173 #define _BIT0 0x00000001
174 #define _BIT1 0x00000002
175 #define _BIT2 0x00000004
176 #define _BIT3 0x00000008
178 #define _BIT4 0x00000010
179 #define _BIT5 0x00000020
180 #define _BIT6 0x00000040
181 #define _BIT7 0x00000080
183 #define _BIT8 0x00000100
184 #define _BIT9 0x00000200
185 #define _BIT10 0x00000400
186 #define _BIT11 0x00000800
188 #define _BIT12 0x00001000
189 #define _BIT13 0x00002000
190 #define _BIT14 0x00004000
191 #define _BIT15 0x00008000
193 #define _BIT16 0x00010000
194 #define _BIT17 0x00020000
195 #define _BIT18 0x00040000
196 #define _BIT19 0x00080000
198 #define _BIT20 0x00100000
199 #define _BIT21 0x00200000
200 #define _BIT22 0x00400000
201 #define _BIT23 0x00800000
203 #define _BIT24 0x01000000
204 #define _BIT25 0x02000000
205 #define _BIT26 0x04000000
206 #define _BIT27 0x08000000
208 #define _BIT28 0x10000000
209 #define _BIT29 0x20000000
210 #define _BIT30 0x40000000
211 #define _BIT31 0x80000000
214 #define CONFIG_SYS_LED_A_BIT (_BIT18)
215 #define CONFIG_SYS_LED_A_SR GPSR0
216 #define CONFIG_SYS_LED_A_CR GPCR0
218 #define CONFIG_SYS_LED_B_BIT (_BIT16)
219 #define CONFIG_SYS_LED_B_SR GPSR1
220 #define CONFIG_SYS_LED_B_CR GPCR1
223 /* LED A: off, LED B: off */
224 #define CONFIG_SYS_GPSR0_VAL (_BIT1+_BIT6+_BIT8+_BIT9+_BIT11+_BIT15+_BIT16+_BIT18)
225 #define CONFIG_SYS_GPSR1_VAL (_BIT0+_BIT1+_BIT16+_BIT24+_BIT25 +_BIT7+_BIT8+_BIT9+_BIT11+_BIT13)
226 #define CONFIG_SYS_GPSR2_VAL (_BIT14+_BIT15+_BIT16)
228 #define CONFIG_SYS_GPCR0_VAL 0x00000000
229 #define CONFIG_SYS_GPCR1_VAL 0x00000000
230 #define CONFIG_SYS_GPCR2_VAL 0x00000000
232 #define CONFIG_SYS_GPDR0_VAL (_BIT1+_BIT6+_BIT8+_BIT9+_BIT11+_BIT15+_BIT16+_BIT17+_BIT18)
233 #define CONFIG_SYS_GPDR1_VAL (_BIT0+_BIT1+_BIT16+_BIT24+_BIT25 +_BIT7+_BIT8+_BIT9+_BIT11+_BIT13)
234 #define CONFIG_SYS_GPDR2_VAL (_BIT14+_BIT15+_BIT16)
236 #define CONFIG_SYS_GAFR0_L_VAL (_BIT22+_BIT24+_BIT31)
237 #define CONFIG_SYS_GAFR0_U_VAL (_BIT15+_BIT17+_BIT19+\
238 _BIT20+_BIT22+_BIT24+_BIT26+_BIT29+_BIT31)
239 #define CONFIG_SYS_GAFR1_L_VAL (_BIT3+_BIT4+_BIT6+_BIT8+_BIT10+_BIT12+_BIT15+_BIT17+_BIT19+\
240 _BIT20+_BIT23+_BIT24+_BIT27+_BIT28+_BIT31)
241 #define CONFIG_SYS_GAFR1_U_VAL (_BIT21+_BIT23+_BIT25+_BIT27+_BIT29+_BIT31)
242 #define CONFIG_SYS_GAFR2_L_VAL (_BIT1+_BIT3+_BIT5+_BIT7+_BIT9+_BIT11+_BIT13+_BIT15+_BIT17+\
243 _BIT19+_BIT21+_BIT23+_BIT25+_BIT27+_BIT29+_BIT31)
244 #define CONFIG_SYS_GAFR2_U_VAL (_BIT1)
246 #define CONFIG_SYS_PSSR_VAL (0x20)
251 #define CONFIG_SYS_MSC0_VAL 0x123c2980
252 #define CONFIG_SYS_MSC1_VAL 0x123c2661
253 #define CONFIG_SYS_MSC2_VAL 0x7ff87ff8
256 /* no sdram/pcmcia here */
257 #define CONFIG_SYS_MDCNFG_VAL 0x00000000
258 #define CONFIG_SYS_MDREFR_VAL 0x00000000
259 #define CONFIG_SYS_MDREFR_VAL_100 0x00000000
260 #define CONFIG_SYS_MDMRS_VAL 0x00000000
263 #define SXCNFG_SETTINGS 0x00000000
266 * PCMCIA and CF Interfaces
269 #define CONFIG_SYS_MECR_VAL 0x00000000
270 #define CONFIG_SYS_MCMEM0_VAL 0x00010504
271 #define CONFIG_SYS_MCMEM1_VAL 0x00010504
272 #define CONFIG_SYS_MCATT0_VAL 0x00010504
273 #define CONFIG_SYS_MCATT1_VAL 0x00010504
274 #define CONFIG_SYS_MCIO0_VAL 0x00004715
275 #define CONFIG_SYS_MCIO1_VAL 0x00004715
279 * FLASH and environment organization
281 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
282 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
284 /* timeout values are in ticks */
285 #define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
286 #define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
289 #define CONFIG_ENV_IS_IN_FLASH 1
290 #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x1C000) /* Addr of Environment Sector */
291 #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
293 #endif /* __CONFIG_H */