include/configs/legoev3.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2016 David Lechner <david@lechnology.com>
   4  *
   5  * Based on da850evm.h
   6  *
   7  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
   8  *
   9  * Based on davinci_dvevm.h. Original Copyrights follow:
  10  *
  11  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
  12  */
  13
  14 #ifndef __CONFIG_H
  15 #define __CONFIG_H
  16
  17 /*
  18  * SoC Configuration
  19  */
  20 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
  21 #define CONFIG_SYS_CLK_FREQ             clk_get(DAVINCI_ARM_CLKID)
  22 #define CONFIG_SYS_OSCIN_FREQ           24000000
  23 #define CONFIG_SYS_TIMERBASE            DAVINCI_TIMER0_BASE
  24 #define CONFIG_SYS_HZ_CLOCK             clk_get(DAVINCI_AUXCLK_CLKID)
  25
  26 /*
  27  * Memory Info
  28  */
  29 #define CONFIG_SYS_MALLOC_LEN   (0x10000 + 1*1024*1024) /* malloc() len */
  30 #define PHYS_SDRAM_1            DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
  31 #define PHYS_SDRAM_1_SIZE       (64 << 20) /* SDRAM size 64MB */
  32 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
  33
  34 /* memtest start addr */
  35 #define CONFIG_SYS_MEMTEST_START        (PHYS_SDRAM_1 + 0x2000000)
  36
  37 /* memtest will be run on 16MB */
  38 #define CONFIG_SYS_MEMTEST_END  (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
  39
  40 #define CONFIG_NR_DRAM_BANKS    1 /* we have 1 bank of DRAM */
  41
  42 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (       \
  43         DAVINCI_SYSCFG_SUSPSRC_TIMER0 |         \
  44         DAVINCI_SYSCFG_SUSPSRC_SPI0 |           \
  45         DAVINCI_SYSCFG_SUSPSRC_UART1 |          \
  46         DAVINCI_SYSCFG_SUSPSRC_I2C)
  47
  48 /*
  49  * PLL configuration
  50  */
  51
  52 #define CONFIG_SYS_DA850_PLL0_PLLM     24
  53 #define CONFIG_SYS_DA850_PLL1_PLLM     21
  54
  55 /*
  56  * DDR2 memory configuration
  57  */
  58 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
  59                                         DV_DDR_PHY_EXT_STRBEN | \
  60                                         (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
  61
  62 #define CONFIG_SYS_DA850_DDR2_SDBCR (           \
  63         (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) |     \
  64         (1 << DV_DDR_SDCR_DDREN_SHIFT) |        \
  65         (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) |      \
  66         (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) |    \
  67         (0x3 << DV_DDR_SDCR_CL_SHIFT) |         \
  68         (0x2 << DV_DDR_SDCR_IBANK_SHIFT) |      \
  69         (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
  70
  71 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
  72 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0
  73
  74 #define CONFIG_SYS_DA850_DDR2_SDTIMR (          \
  75         (14 << DV_DDR_SDTMR1_RFC_SHIFT) |       \
  76         (2 << DV_DDR_SDTMR1_RP_SHIFT) |         \
  77         (2 << DV_DDR_SDTMR1_RCD_SHIFT) |        \
  78         (1 << DV_DDR_SDTMR1_WR_SHIFT) |         \
  79         (5 << DV_DDR_SDTMR1_RAS_SHIFT) |        \
  80         (8 << DV_DDR_SDTMR1_RC_SHIFT) |         \
  81         (1 << DV_DDR_SDTMR1_RRD_SHIFT) |        \
  82         (0 << DV_DDR_SDTMR1_WTR_SHIFT))
  83
  84 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 (         \
  85         (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) |     \
  86         (0 << DV_DDR_SDTMR2_XP_SHIFT) |         \
  87         (0 << DV_DDR_SDTMR2_ODT_SHIFT) |        \
  88         (17 << DV_DDR_SDTMR2_XSNR_SHIFT) |      \
  89         (199 << DV_DDR_SDTMR2_XSRD_SHIFT) |     \
  90         (0 << DV_DDR_SDTMR2_RTP_SHIFT) |        \
  91         (0 << DV_DDR_SDTMR2_CKE_SHIFT))
  92
  93 #define CONFIG_SYS_DA850_DDR2_SDRCR    0x00000494
  94 #define CONFIG_SYS_DA850_DDR2_PBBPR    0x30
  95
  96 /*
  97  * Serial Driver info
  98  */
  99 #define CONFIG_SYS_NS16550_SERIAL
 100 #define CONFIG_SYS_NS16550_REG_SIZE     -4      /* NS16550 register size */
 101 #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART1_BASE /* Base address of UART1 */
 102 #define CONFIG_SYS_NS16550_CLK  clk_get(DAVINCI_UART2_CLKID)
 103
 104 #define CONFIG_SYS_SPI_BASE             DAVINCI_SPI0_BASE
 105 #define CONFIG_SYS_SPI_CLK              clk_get(DAVINCI_SPI0_CLKID)
 106 #define CONFIG_SF_DEFAULT_SPEED         50000000
 107 #define CONFIG_ENV_SPI_MAX_HZ           CONFIG_SF_DEFAULT_SPEED
 108
 109 /*
 110  * I2C Configuration
 111  */
 112 #define CONFIG_SYS_I2C
 113 #define CONFIG_SYS_I2C_DAVINCI
 114 #define CONFIG_SYS_DAVINCI_I2C_SPEED            400000
 115 #define CONFIG_SYS_DAVINCI_I2C_SLAVE   10 /* Bogus, master-only in U-Boot */
 116
 117 /*
 118  * U-Boot general configuration
 119  */
 120 #define CONFIG_BOOTFILE         "uImage" /* Boot file name */
 121 #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 122 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
 123 #define CONFIG_SYS_LOAD_ADDR    (PHYS_SDRAM_1 + 0x700000)
 124 #define CONFIG_MX_CYCLIC
 125
 126 /*
 127  * Linux Information
 128  */
 129 #define LINUX_BOOT_PARAM_ADDR   (PHYS_SDRAM_1 + 0x100)
 130 #define CONFIG_HWCONFIG         /* enable hwconfig */
 131 #define CONFIG_CMDLINE_TAG
 132 #define CONFIG_REVISION_TAG
 133 #define CONFIG_SERIAL_TAG
 134 #define CONFIG_SETUP_MEMORY_TAGS
 135 #define CONFIG_SETUP_INITRD_TAG
 136 #define CONFIG_BOOTCOMMAND \
 137         "if mmc rescan; then " \
 138                 "if run loadbootscr; then " \
 139                         "run bootscript; " \
 140                 "else " \
 141                         "if run loadimage; then " \
 142                                 "run mmcargs; " \
 143                                 "run mmcboot; " \
 144                         "else " \
 145                                 "run flashargs; " \
 146                                 "run flashboot; " \
 147                         "fi; " \
 148                 "fi; " \
 149         "else " \
 150                 "run flashargs; " \
 151                 "run flashboot; " \
 152         "fi"
 153 #define CONFIG_EXTRA_ENV_SETTINGS \
 154         "memsize=64M\0" \
 155         "filesyssize=10M\0" \
 156         "verify=n\0" \
 157         "console=ttyS1,115200n8\0" \
 158         "bootscraddr=0xC0600000\0" \
 159         "loadaddr=0xC0007FC0\0" \
 160         "filesysaddr=0xC1180000\0" \
 161         "fwupdateboot=mw 0xFFFF1FFC 0x5555AAAA; reset\0" \
 162         "mmcargs=setenv bootargs mem=${memsize} console=${console} root=/dev/mmcblk0p2 rw rootwait lpj=747520\0" \
 163         "mmcboot=bootm ${loadaddr}\0" \
 164         "flashargs=setenv bootargs mem=${memsize} initrd=${filesysaddr},${filesyssize} root=/dev/ram0 rw rootfstype=squashfs console=${console} lpj=747520\0" \
 165         "flashboot=sf probe 0; sf read ${loadaddr} 0x50000 0x400000; sf read ${filesysaddr} 0x450000 0xA00000; bootm ${loadaddr}\0" \
 166         "loadimage=fatload mmc 0 ${loadaddr} uImage\0" \
 167         "loadbootscr=fatload mmc 0 ${bootscraddr} boot.scr\0" \
 168         "bootscript=source ${bootscraddr}\0" \
 169
 170 #ifdef CONFIG_CMD_BDI
 171 #define CONFIG_CLOCKS
 172 #endif
 173
 174 #define CONFIG_ENV_SIZE         (16 << 10)
 175
 176 /* additions for new relocation code, must added to all boards */
 177 #define CONFIG_SYS_SDRAM_BASE           0xc0000000
 178
 179 #define CONFIG_SYS_INIT_SP_ADDR         0x80010000
 180
 181 #include <asm/arch/hardware.h>
 182
 183 #endif /* __CONFIG_H */