include/configs/kmvect1.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   4  *                    Dave Liu <daveliu@freescale.com>
   5  *
   6  * Copyright (C) 2007 Logic Product Development, Inc.
   7  *                    Peter Barada <peterb@logicpd.com>
   8  *
   9  * Copyright (C) 2007 MontaVista Software, Inc.
  10  *                    Anton Vorontsov <avorontsov@ru.mvista.com>
  11  *
  12  * (C) Copyright 2010
  13  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  14  */
  15
  16 #ifndef __CONFIG_H
  17 #define __CONFIG_H
  18
  19 /*
  20  * High Level Configuration Options
  21  */
  22
  23 #define CONFIG_HOSTNAME         "kmvect1"
  24 #define CONFIG_KM_BOARD_NAME   "kmvect1"
  25 /* at end of uboot partition, before env */
  26 #define CONFIG_SYS_QE_FW_ADDR   0xF00B0000
  27
  28 /*
  29  * High Level Configuration Options
  30  */
  31 #define CONFIG_E300             1       /* E300 family */
  32 #define CONFIG_QE               1       /* Has QE */
  33
  34 #define CONFIG_KM_DEF_ARCH      "arch=ppc_82xx\0"
  35
  36 /* include common defines/options for all Keymile boards */
  37 #include "km/keymile-common.h"
  38 #include "km/km-powerpc.h"
  39
  40 /*
  41  * System Clock Setup
  42  */
  43 #define CONFIG_83XX_CLKIN               66000000
  44 #define CONFIG_SYS_CLK_FREQ             66000000
  45 #define CONFIG_83XX_PCICLK              66000000
  46
  47 /*
  48  * IMMR new address
  49  */
  50 #define CONFIG_SYS_IMMR         0xE0000000
  51
  52 /*
  53  * Bus Arbitration Configuration Register (ACR)
  54  */
  55 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* pipeline depth 4 transactions */
  56 #define CONFIG_SYS_ACR_RPTCNT   3       /* 4 consecutive transactions */
  57 #define CONFIG_SYS_ACR_APARK    0       /* park bus to master (below) */
  58 #define CONFIG_SYS_ACR_PARKM    3       /* parking master = QuiccEngine */
  59
  60 /*
  61  * DDR Setup
  62  */
  63 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
  64 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  65 #define CONFIG_SYS_SDRAM_BASE2  (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
  66
  67 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  68 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN | \
  69                                         DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  70
  71 #define CFG_83XX_DDR_USES_CS0
  72
  73 /*
  74  * Manually set up DDR parameters
  75  */
  76 #define CONFIG_DDR_II
  77 #define CONFIG_SYS_DDR_SIZE             2048 /* MB */
  78
  79 /*
  80  * The reserved memory
  81  */
  82 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  83 #define CONFIG_SYS_FLASH_BASE           0xF0000000
  84
  85 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  86 #define CONFIG_SYS_RAMBOOT
  87 #endif
  88
  89 /* Reserve 768 kB for Mon */
  90 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
  91
  92 /*
  93  * Initial RAM Base Address Setup
  94  */
  95 #define CONFIG_SYS_INIT_RAM_LOCK
  96 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
  97 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* End of used area in RAM */
  98 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
  99                                                 GENERATED_GBL_DATA_SIZE)
 100
 101 /*
 102  * Init Local Bus Memory Controller:
 103  *
 104  * Bank Bus     Machine PortSz  Size  Device
 105  * ---- ---     ------- ------  -----  ------
 106  *  0   Local   GPCM    16 bit  256MB FLASH
 107  *  1   Local   GPCM     8 bit  128MB GPIO/PIGGY
 108  *
 109  */
 110 /*
 111  * FLASH on the Local Bus
 112  */
 113 #define CONFIG_SYS_FLASH_SIZE           256 /* max FLASH size is 256M */
 114
 115 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 116 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_256MB)
 117
 118 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE | \
 119                                 BR_PS_16 | /* 16 bit port size */ \
 120                                 BR_MS_GPCM | /* MSEL = GPCM */ \
 121                                 BR_V)
 122
 123 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
 124                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 125                                 OR_GPCM_SCY_5 | \
 126                                 OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 127
 128 #define CONFIG_SYS_MAX_FLASH_BANKS      1   /* max num of flash banks   */
 129 #define CONFIG_SYS_MAX_FLASH_SECT       512 /* max num of sects on one chip */
 130 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
 131
 132 /*
 133  * PRIO1/PIGGY on the local bus CS1
 134  */
 135 /* Window base at flash base */
 136 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_KMBEC_FPGA_BASE
 137 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_128MB)
 138
 139 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_KMBEC_FPGA_BASE | \
 140                                 BR_PS_8 | /* 8 bit port size */ \
 141                                 BR_MS_GPCM | /* MSEL = GPCM */ \
 142                                 BR_V)
 143 #define CONFIG_SYS_OR1_PRELIM   (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \
 144                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 145                                 OR_GPCM_SCY_2 | \
 146                                 OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 147
 148 /*
 149  * Serial Port
 150  */
 151 #define CONFIG_SYS_NS16550_SERIAL
 152 #define CONFIG_SYS_NS16550_REG_SIZE     1
 153 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 154
 155 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 156 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 157
 158 /*
 159  * QE UEC ethernet configuration
 160  */
 161 #define CONFIG_UEC_ETH
 162 #define CONFIG_ETHPRIME         "UEC0"
 163
 164 #ifdef CONFIG_UEC_ETH1
 165 #define CONFIG_SYS_UEC1_UCC_NUM 3       /* UCC4 */
 166 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK_NONE /* not used in RMII Mode */
 167 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK17
 168 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 169 #define CONFIG_SYS_UEC1_PHY_ADDR        0
 170 #define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_RMII
 171 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 172 #endif
 173
 174 /*
 175  * Environment
 176  */
 177
 178 #ifndef CONFIG_SYS_RAMBOOT
 179 #ifndef CONFIG_ENV_ADDR
 180 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 181                                         CONFIG_SYS_MONITOR_LEN)
 182 #endif
 183 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 184 #ifndef CONFIG_ENV_OFFSET
 185 #define CONFIG_ENV_OFFSET       (CONFIG_SYS_MONITOR_LEN)
 186 #endif
 187
 188 /* Address and size of Redundant Environment Sector     */
 189 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + \
 190                                                 CONFIG_ENV_SECT_SIZE)
 191 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 192
 193 #else /* CFG_SYS_RAMBOOT */
 194 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 195 #define CONFIG_ENV_SIZE         0x2000
 196 #endif /* CFG_SYS_RAMBOOT */
 197
 198 /* I2C */
 199 #define CONFIG_SYS_I2C
 200 #define CONFIG_SYS_NUM_I2C_BUSES        4
 201 #define CONFIG_SYS_I2C_MAX_HOPS         1
 202 #define CONFIG_SYS_I2C_FSL
 203 #define CONFIG_SYS_FSL_I2C_SPEED        200000
 204 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 205 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 206 #define CONFIG_SYS_I2C_OFFSET           0x3000
 207 #define CONFIG_SYS_FSL_I2C2_SPEED       200000
 208 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 209 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 210 #define CONFIG_SYS_I2C_BUSES    {{0, {I2C_NULL_HOP} }, \
 211                 {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
 212                 {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
 213                 {1, {I2C_NULL_HOP} } }
 214
 215 #define CONFIG_KM_IVM_BUS               2       /* I2C2 (Mux-Port 1)*/
 216
 217 #if defined(CONFIG_CMD_NAND)
 218 #define CONFIG_NAND_KMETER1
 219 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 220 #define CONFIG_SYS_NAND_BASE            CONFIG_SYS_KMBEC_FPGA_BASE
 221 #endif
 222
 223 /*
 224  * For booting Linux, the board info and command line data
 225  * have to be in the first 8 MB of memory, since this is
 226  * the maximum mapped by the Linux kernel during initialization.
 227  */
 228 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)
 229
 230 /*
 231  * Core HID Setup
 232  */
 233 #define CONFIG_SYS_HID0_INIT            0x000000000
 234 #define CONFIG_SYS_HID0_FINAL           (HID0_ENABLE_MACHINE_CHECK | \
 235                                          HID0_ENABLE_INSTRUCTION_CACHE)
 236 #define CONFIG_SYS_HID2                 HID2_HBE
 237
 238 /*
 239  * MMU Setup
 240  */
 241
 242 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 243
 244 /* DDR: cache cacheable */
 245 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
 246                                 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 247 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
 248                                         BATU_VS | BATU_VP)
 249 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 250 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 251
 252 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
 253 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR | BATL_PP_RW | \
 254                                 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 255 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \
 256                                         | BATU_VP)
 257 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 258 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 259
 260 /* PRIO1, PIGGY:  icache cacheable, but dcache-inhibit and guarded */
 261 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
 262                                 BATL_MEMCOHERENCE)
 263 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \
 264                                 BATU_VS | BATU_VP)
 265 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
 266                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 267 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 268
 269 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 270 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
 271                                         BATL_MEMCOHERENCE)
 272 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \
 273                                         BATU_VS | BATU_VP)
 274 #define CONFIG_SYS_DBAT3L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
 275                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 276 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 277
 278 /* Stack in dcache: cacheable, no memory coherence */
 279 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 280 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
 281                                         BATU_VS | BATU_VP)
 282 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 283 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 284
 285 /*
 286  * Internal Definitions
 287  */
 288 #define BOOTFLASH_START 0xF0000000
 289
 290 #define CONFIG_KM_CONSOLE_TTY   "ttyS0"
 291
 292 /*
 293  * Environment Configuration
 294  */
 295 #define CONFIG_ENV_OVERWRITE
 296 #ifndef CONFIG_KM_DEF_ENV               /* if not set by keymile-common.h */
 297 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
 298 #endif
 299
 300 #ifndef CONFIG_KM_DEF_ARCH
 301 #define CONFIG_KM_DEF_ARCH      "arch=ppc_82xx\0"
 302 #endif
 303
 304 #define CONFIG_EXTRA_ENV_SETTINGS \
 305         CONFIG_KM_DEF_ENV                                               \
 306         CONFIG_KM_DEF_ARCH                                              \
 307         "newenv="                                                       \
 308                 "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && "  \
 309                 "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0"         \
 310         "unlock=yes\0"                                                  \
 311         ""
 312
 313 #if defined(CONFIG_UEC_ETH)
 314 #define CONFIG_HAS_ETH0
 315 #endif
 316
 317 /* QE microcode/firmware address */
 318 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 319 /* between the u-boot partition and env */
 320 #ifndef CONFIG_SYS_QE_FW_ADDR
 321 #define CONFIG_SYS_QE_FW_ADDR   0xF00C0000
 322 #endif
 323
 324 /*
 325  * System IO Config
 326  */
 327 /* 0x14000180 SICR_1 */
 328 #define CONFIG_SYS_SICRL (0                     \
 329                 | SICR_1_UART1_UART1RTS         \
 330                 | SICR_1_I2C_CKSTOP             \
 331                 | SICR_1_IRQ_A_IRQ              \
 332                 | SICR_1_IRQ_B_IRQ              \
 333                 | SICR_1_GPIO_A_GPIO            \
 334                 | SICR_1_GPIO_B_GPIO            \
 335                 | SICR_1_GPIO_C_GPIO            \
 336                 | SICR_1_GPIO_D_GPIO            \
 337                 | SICR_1_GPIO_E_GPIO            \
 338                 | SICR_1_GPIO_F_GPIO            \
 339                 | SICR_1_USB_A_UART2S           \
 340                 | SICR_1_USB_B_UART2RTS         \
 341                 | SICR_1_FEC1_FEC1              \
 342                 | SICR_1_FEC2_FEC2              \
 343                 )
 344
 345 /* 0x00080400 SICR_2 */
 346 #define CONFIG_SYS_SICRH (0                     \
 347                 | SICR_2_FEC3_FEC3              \
 348                 | SICR_2_HDLC1_A_HDLC1          \
 349                 | SICR_2_ELBC_A_LA              \
 350                 | SICR_2_ELBC_B_LCLK            \
 351                 | SICR_2_HDLC2_A_HDLC2          \
 352                 | SICR_2_USB_D_GPIO             \
 353                 | SICR_2_PCI_PCI                \
 354                 | SICR_2_HDLC1_B_HDLC1          \
 355                 | SICR_2_HDLC1_C_HDLC1          \
 356                 | SICR_2_HDLC2_B_GPIO           \
 357                 | SICR_2_HDLC2_C_HDLC2          \
 358                 | SICR_2_QUIESCE_B              \
 359                 )
 360
 361 /* GPR_1 */
 362 #define CONFIG_SYS_GPR1  0x50008060
 363
 364 #define CONFIG_SYS_GP1DIR 0x00000000
 365 #define CONFIG_SYS_GP1ODR 0x00000000
 366 #define CONFIG_SYS_GP2DIR 0xFF000000
 367 #define CONFIG_SYS_GP2ODR 0x00000000
 368
 369 /*
 370  * Hardware Reset Configuration Word
 371  */
 372 #define CONFIG_SYS_HRCW_LOW (\
 373         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
 374         HRCWL_DDR_TO_SCB_CLK_2X1 | \
 375         HRCWL_CSB_TO_CLKIN_2X1 | \
 376         HRCWL_CORE_TO_CSB_2X1 | \
 377         HRCWL_CE_PLL_VCO_DIV_2 | \
 378         HRCWL_CE_TO_PLL_1X3)
 379
 380 #define CONFIG_SYS_HRCW_HIGH (\
 381         HRCWH_PCI_AGENT | \
 382         HRCWH_PCI_ARBITER_DISABLE | \
 383         HRCWH_CORE_ENABLE | \
 384         HRCWH_FROM_0X00000100 | \
 385         HRCWH_BOOTSEQ_DISABLE | \
 386         HRCWH_SW_WATCHDOG_DISABLE | \
 387         HRCWH_ROM_LOC_LOCAL_16BIT | \
 388         HRCWH_BIG_ENDIAN | \
 389         HRCWH_LALE_NORMAL)
 390
 391 #define CONFIG_SYS_DDRCDR (\
 392         DDRCDR_EN | \
 393         DDRCDR_PZ_MAXZ | \
 394         DDRCDR_NZ_MAXZ | \
 395         DDRCDR_M_ODR)
 396
 397 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000007f
 398 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
 399                                          SDRAM_CFG_32_BE | \
 400                                          SDRAM_CFG_SREN | \
 401                                          SDRAM_CFG_HSE)
 402
 403 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
 404 #define CONFIG_SYS_DDR_CLK_CNTL         (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 405 #define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
 406                                  (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
 407
 408 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN | CSCONFIG_AP | \
 409                                          CSCONFIG_ODT_RD_NEVER | \
 410                                          CSCONFIG_ODT_WR_ONLY_CURRENT | \
 411                                          CSCONFIG_ROW_BIT_13 | \
 412                                          CSCONFIG_COL_BIT_10)
 413
 414 #define CONFIG_SYS_DDR_MODE     0x47860242
 415 #define CONFIG_SYS_DDR_MODE2    0x8080c000
 416
 417 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
 418                                  (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
 419                                  (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
 420                                  (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
 421                                  (0 << TIMING_CFG0_WWT_SHIFT) | \
 422                                  (0 << TIMING_CFG0_RRT_SHIFT) | \
 423                                  (0 << TIMING_CFG0_WRT_SHIFT) | \
 424                                  (0 << TIMING_CFG0_RWT_SHIFT))
 425
 426 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
 427                                  (2 << TIMING_CFG1_WRTORD_SHIFT) | \
 428                                  (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
 429                                  (3 << TIMING_CFG1_WRREC_SHIFT) | \
 430                                  (7 << TIMING_CFG1_REFREC_SHIFT) | \
 431                                  (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
 432                                  (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
 433                                  (3 << TIMING_CFG1_PRETOACT_SHIFT))
 434
 435 #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
 436                                  (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
 437                                  (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
 438                                  (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
 439                                  (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
 440                                  (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
 441                                  (5 << TIMING_CFG2_CPO_SHIFT))
 442
 443 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 444
 445 #define CONFIG_SYS_KMBEC_FPGA_BASE      0xE8000000
 446 #define CONFIG_SYS_KMBEC_FPGA_SIZE      128
 447
 448 /* EEprom support */
 449 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 450
 451 /*
 452  * Local Bus Configuration & Clock Setup
 453  */
 454 #define CONFIG_SYS_LCRR_DBYP    0x80000000
 455 #define CONFIG_SYS_LCRR_EADC    0x00010000
 456 #define CONFIG_SYS_LCRR_CLKDIV  0x00000002
 457
 458 #define CONFIG_SYS_LBC_LBCR     0x00000000
 459
 460 /*
 461  * MMU Setup
 462  */
 463 #define CONFIG_SYS_IBAT7L       (0)
 464 #define CONFIG_SYS_IBAT7U       (0)
 465 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 466 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 467
 468 #define CONFIG_SYS_APP1_BASE            0xA0000000
 469 #define CONFIG_SYS_APP1_SIZE            256 /* Megabytes */
 470 #define CONFIG_SYS_APP2_BASE            0xB0000000
 471 #define CONFIG_SYS_APP2_SIZE            256 /* Megabytes */
 472
 473 /* EEprom support */
 474 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 475
 476 /*
 477  * Init Local Bus Memory Controller:
 478  *
 479  * Bank Bus     Machine PortSz  Size  Device
 480  * ---- ---     ------- ------  -----  ------
 481  *  2   Local   UPMA    16 bit  256MB APP1
 482  *  3   Local   GPCM    16 bit  256MB APP2
 483  *
 484  */
 485
 486 /*
 487  * APP1 on the local bus CS2
 488  */
 489 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_APP1_BASE
 490 #define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_256MB)
 491
 492 #define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_APP1_BASE | \
 493                                  BR_PS_16 | \
 494                                  BR_MS_UPMA | \
 495                                  BR_V)
 496 #define CONFIG_SYS_OR2_PRELIM   (MEG_TO_AM(CONFIG_SYS_APP1_SIZE))
 497
 498 #define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_APP2_BASE | \
 499                                  BR_PS_16 | \
 500                                  BR_V)
 501
 502 #define CONFIG_SYS_OR3_PRELIM   (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
 503                                  OR_GPCM_CSNT | \
 504                                  OR_GPCM_ACS_DIV4 | \
 505                                  OR_GPCM_SCY_3 | \
 506                                  OR_GPCM_TRLX_SET)
 507
 508 #define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \
 509                          0x0000c000 | \
 510                          MxMR_WLFx_2X)
 511
 512 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_APP2_BASE
 513 #define CONFIG_SYS_LBLAWAR3_PRELIM      (LBLAWAR_EN | LBLAWAR_256MB)
 514
 515 /*
 516  * MMU Setup
 517  */
 518 /* APP1:  icache cacheable, but dcache-inhibit and guarded */
 519 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \
 520                                  BATL_MEMCOHERENCE)
 521 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_APP1_BASE | BATU_BL_256M | \
 522                                  BATU_VS | BATU_VP)
 523 #define CONFIG_SYS_DBAT5L       (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \
 524                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 525 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 526 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \
 527                                  BATL_MEMCOHERENCE)
 528 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_APP2_BASE | BATU_BL_256M | \
 529                                  BATU_VS | BATU_VP)
 530 #define CONFIG_SYS_DBAT6L       (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \
 531                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 532 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 533
 534 /*
 535  * QE UEC ethernet configuration
 536  */
 537 #define CONFIG_MV88E6352_SWITCH
 538 #define CONFIG_KM_MVEXTSW_ADDR          0x10
 539
 540 /* ethernet port connected to simple switch 88e6122 (UEC0) */
 541 #define CONFIG_UEC_ETH1
 542 #define CONFIG_SYS_UEC1_UCC_NUM         0       /* UCC1 */
 543 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK9
 544 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK10
 545
 546 #define CONFIG_FIXED_PHY                0xFFFFFFFF
 547 #define CONFIG_SYS_FIXED_PHY_ADDR       0x1E    /* unused address */
 548 #define CONFIG_SYS_FIXED_PHY_PORT(devnum, speed, duplex) \
 549                 {devnum, speed, duplex}
 550 #define CONFIG_SYS_FIXED_PHY_PORTS \
 551                 CONFIG_SYS_FIXED_PHY_PORT("UEC0", SPEED_100, DUPLEX_FULL)
 552
 553 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 554 #define CONFIG_SYS_UEC1_PHY_ADDR        CONFIG_SYS_FIXED_PHY_ADDR
 555 #define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
 556 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 557
 558 /* ethernet port connected to piggy (UEC2) */
 559 #define CONFIG_HAS_ETH1
 560 #define CONFIG_UEC_ETH2
 561 #define CONFIG_SYS_UEC2_UCC_NUM         2       /* UCC3 */
 562 #define CONFIG_SYS_UEC2_RX_CLK          QE_CLK_NONE /* not used in RMII Mode */
 563 #define CONFIG_SYS_UEC2_TX_CLK          QE_CLK12
 564 #define CONFIG_SYS_UEC2_ETH_TYPE        FAST_ETH
 565 #define CONFIG_SYS_UEC2_PHY_ADDR        0
 566 #define CONFIG_SYS_UEC2_INTERFACE_TYPE  PHY_INTERFACE_MODE_RMII
 567 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
 568
 569 #endif /* __CONFIG_H */