include/configs/kmvect1.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   4  *                    Dave Liu <daveliu@freescale.com>
   5  *
   6  * Copyright (C) 2007 Logic Product Development, Inc.
   7  *                    Peter Barada <peterb@logicpd.com>
   8  *
   9  * Copyright (C) 2007 MontaVista Software, Inc.
  10  *                    Anton Vorontsov <avorontsov@ru.mvista.com>
  11  *
  12  * (C) Copyright 2010
  13  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  14  */
  15
  16 #ifndef __CONFIG_H
  17 #define __CONFIG_H
  18
  19 /*
  20  * High Level Configuration Options
  21  */
  22
  23 #define CONFIG_HOSTNAME         "kmvect1"
  24 #define CONFIG_KM_BOARD_NAME   "kmvect1"
  25 /* at end of uboot partition, before env */
  26 #define CONFIG_SYS_QE_FW_ADDR   0xF00B0000
  27
  28 /*
  29  * High Level Configuration Options
  30  */
  31 #define CONFIG_E300             1       /* E300 family */
  32 #define CONFIG_QE               1       /* Has QE */
  33
  34 #define CONFIG_KM_DEF_ARCH      "arch=ppc_82xx\0"
  35
  36 /* include common defines/options for all Keymile boards */
  37 #include "km/keymile-common.h"
  38 #include "km/km-powerpc.h"
  39
  40 /*
  41  * System Clock Setup
  42  */
  43 #define CONFIG_83XX_CLKIN               66000000
  44 #define CONFIG_SYS_CLK_FREQ             66000000
  45 #define CONFIG_83XX_PCICLK              66000000
  46
  47 /*
  48  * IMMR new address
  49  */
  50 #define CONFIG_SYS_IMMR         0xE0000000
  51
  52 /*
  53  * Bus Arbitration Configuration Register (ACR)
  54  */
  55 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* pipeline depth 4 transactions */
  56 #define CONFIG_SYS_ACR_RPTCNT   3       /* 4 consecutive transactions */
  57 #define CONFIG_SYS_ACR_APARK    0       /* park bus to master (below) */
  58 #define CONFIG_SYS_ACR_PARKM    3       /* parking master = QuiccEngine */
  59
  60 /*
  61  * DDR Setup
  62  */
  63 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
  64 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  65 #define CONFIG_SYS_SDRAM_BASE2  (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
  66
  67 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  68 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN | \
  69                                         DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  70
  71 #define CFG_83XX_DDR_USES_CS0
  72
  73 /*
  74  * Manually set up DDR parameters
  75  */
  76 #define CONFIG_DDR_II
  77 #define CONFIG_SYS_DDR_SIZE             2048 /* MB */
  78
  79 /*
  80  * The reserved memory
  81  */
  82 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  83 #define CONFIG_SYS_FLASH_BASE           0xF0000000
  84
  85 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  86 #define CONFIG_SYS_RAMBOOT
  87 #endif
  88
  89 /* Reserve 768 kB for Mon */
  90 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
  91
  92 /*
  93  * Initial RAM Base Address Setup
  94  */
  95 #define CONFIG_SYS_INIT_RAM_LOCK
  96 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
  97 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* End of used area in RAM */
  98 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
  99                                                 GENERATED_GBL_DATA_SIZE)
 100
 101 /*
 102  * Init Local Bus Memory Controller:
 103  *
 104  * Bank Bus     Machine PortSz  Size  Device
 105  * ---- ---     ------- ------  -----  ------
 106  *  0   Local   GPCM    16 bit  256MB FLASH
 107  *  1   Local   GPCM     8 bit  128MB GPIO/PIGGY
 108  *
 109  */
 110 /*
 111  * FLASH on the Local Bus
 112  */
 113 #define CONFIG_SYS_FLASH_SIZE           256 /* max FLASH size is 256M */
 114
 115 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 116 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_256MB)
 117
 118 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE | \
 119                                 BR_PS_16 | /* 16 bit port size */ \
 120                                 BR_MS_GPCM | /* MSEL = GPCM */ \
 121                                 BR_V)
 122
 123 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
 124                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 125                                 OR_GPCM_SCY_5 | \
 126                                 OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 127
 128 #define CONFIG_SYS_MAX_FLASH_BANKS      1   /* max num of flash banks   */
 129 #define CONFIG_SYS_MAX_FLASH_SECT       512 /* max num of sects on one chip */
 130 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
 131
 132 /*
 133  * PRIO1/PIGGY on the local bus CS1
 134  */
 135 /* Window base at flash base */
 136 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_KMBEC_FPGA_BASE
 137 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_128MB)
 138
 139 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_KMBEC_FPGA_BASE | \
 140                                 BR_PS_8 | /* 8 bit port size */ \
 141                                 BR_MS_GPCM | /* MSEL = GPCM */ \
 142                                 BR_V)
 143 #define CONFIG_SYS_OR1_PRELIM   (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \
 144                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 145                                 OR_GPCM_SCY_2 | \
 146                                 OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 147
 148 /*
 149  * Serial Port
 150  */
 151 #define CONFIG_SYS_NS16550_SERIAL
 152 #define CONFIG_SYS_NS16550_REG_SIZE     1
 153 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 154
 155 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 156 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 157
 158 /*
 159  * QE UEC ethernet configuration
 160  */
 161 #define CONFIG_UEC_ETH
 162 #define CONFIG_ETHPRIME         "UEC0"
 163
 164 #ifdef CONFIG_UEC_ETH1
 165 #define CONFIG_SYS_UEC1_UCC_NUM 3       /* UCC4 */
 166 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK_NONE /* not used in RMII Mode */
 167 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK17
 168 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 169 #define CONFIG_SYS_UEC1_PHY_ADDR        0
 170 #define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_RMII
 171 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 172 #endif
 173
 174 /*
 175  * Environment
 176  */
 177
 178 #ifndef CONFIG_SYS_RAMBOOT
 179 #ifndef CONFIG_ENV_ADDR
 180 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 181                                         CONFIG_SYS_MONITOR_LEN)
 182 #endif
 183 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 184 #ifndef CONFIG_ENV_OFFSET
 185 #define CONFIG_ENV_OFFSET       (CONFIG_SYS_MONITOR_LEN)
 186 #endif
 187
 188 /* Address and size of Redundant Environment Sector     */
 189 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + \
 190                                                 CONFIG_ENV_SECT_SIZE)
 191 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 192
 193 #else /* CFG_SYS_RAMBOOT */
 194 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 195 #define CONFIG_ENV_SIZE         0x2000
 196 #endif /* CFG_SYS_RAMBOOT */
 197
 198 /* I2C */
 199 #define CONFIG_SYS_I2C
 200 #define CONFIG_SYS_NUM_I2C_BUSES        4
 201 #define CONFIG_SYS_I2C_MAX_HOPS         1
 202 #define CONFIG_SYS_I2C_FSL
 203 #define CONFIG_SYS_FSL_I2C_SPEED        200000
 204 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 205 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 206 #define CONFIG_SYS_I2C_OFFSET           0x3000
 207 #define CONFIG_SYS_FSL_I2C2_SPEED       200000
 208 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 209 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 210 #define CONFIG_SYS_I2C_BUSES    {{0, {I2C_NULL_HOP} }, \
 211                 {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
 212                 {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
 213                 {1, {I2C_NULL_HOP} } }
 214
 215 #define CONFIG_KM_IVM_BUS               2       /* I2C2 (Mux-Port 1)*/
 216
 217 #if defined(CONFIG_CMD_NAND)
 218 #define CONFIG_NAND_KMETER1
 219 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 220 #define CONFIG_SYS_NAND_BASE            CONFIG_SYS_KMBEC_FPGA_BASE
 221 #endif
 222
 223 /*
 224  * For booting Linux, the board info and command line data
 225  * have to be in the first 8 MB of memory, since this is
 226  * the maximum mapped by the Linux kernel during initialization.
 227  */
 228 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)
 229
 230 /*
 231  * Core HID Setup
 232  */
 233 #define CONFIG_SYS_HID0_INIT            0x000000000
 234 #define CONFIG_SYS_HID0_FINAL           (HID0_ENABLE_MACHINE_CHECK | \
 235                                          HID0_ENABLE_INSTRUCTION_CACHE)
 236 #define CONFIG_SYS_HID2                 HID2_HBE
 237
 238 /*
 239  * MMU Setup
 240  */
 241
 242 /* DDR: cache cacheable */
 243 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
 244                                 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 245 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
 246                                         BATU_VS | BATU_VP)
 247 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 248 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 249
 250 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
 251 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR | BATL_PP_RW | \
 252                                 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 253 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \
 254                                         | BATU_VP)
 255 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 256 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 257
 258 /* PRIO1, PIGGY:  icache cacheable, but dcache-inhibit and guarded */
 259 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
 260                                 BATL_MEMCOHERENCE)
 261 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \
 262                                 BATU_VS | BATU_VP)
 263 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
 264                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 265 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 266
 267 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 268 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
 269                                         BATL_MEMCOHERENCE)
 270 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \
 271                                         BATU_VS | BATU_VP)
 272 #define CONFIG_SYS_DBAT3L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
 273                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 274 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 275
 276 /* Stack in dcache: cacheable, no memory coherence */
 277 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 278 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
 279                                         BATU_VS | BATU_VP)
 280 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 281 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 282
 283 /*
 284  * Internal Definitions
 285  */
 286 #define BOOTFLASH_START 0xF0000000
 287
 288 #define CONFIG_KM_CONSOLE_TTY   "ttyS0"
 289
 290 /*
 291  * Environment Configuration
 292  */
 293 #define CONFIG_ENV_OVERWRITE
 294 #ifndef CONFIG_KM_DEF_ENV               /* if not set by keymile-common.h */
 295 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
 296 #endif
 297
 298 #ifndef CONFIG_KM_DEF_ARCH
 299 #define CONFIG_KM_DEF_ARCH      "arch=ppc_82xx\0"
 300 #endif
 301
 302 #define CONFIG_EXTRA_ENV_SETTINGS \
 303         CONFIG_KM_DEF_ENV                                               \
 304         CONFIG_KM_DEF_ARCH                                              \
 305         "newenv="                                                       \
 306                 "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && "  \
 307                 "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0"         \
 308         "unlock=yes\0"                                                  \
 309         ""
 310
 311 #if defined(CONFIG_UEC_ETH)
 312 #define CONFIG_HAS_ETH0
 313 #endif
 314
 315 /* QE microcode/firmware address */
 316 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 317 /* between the u-boot partition and env */
 318 #ifndef CONFIG_SYS_QE_FW_ADDR
 319 #define CONFIG_SYS_QE_FW_ADDR   0xF00C0000
 320 #endif
 321
 322 /*
 323  * System IO Config
 324  */
 325 /* 0x14000180 SICR_1 */
 326 #define CONFIG_SYS_SICRL (0                     \
 327                 | SICR_1_UART1_UART1RTS         \
 328                 | SICR_1_I2C_CKSTOP             \
 329                 | SICR_1_IRQ_A_IRQ              \
 330                 | SICR_1_IRQ_B_IRQ              \
 331                 | SICR_1_GPIO_A_GPIO            \
 332                 | SICR_1_GPIO_B_GPIO            \
 333                 | SICR_1_GPIO_C_GPIO            \
 334                 | SICR_1_GPIO_D_GPIO            \
 335                 | SICR_1_GPIO_E_GPIO            \
 336                 | SICR_1_GPIO_F_GPIO            \
 337                 | SICR_1_USB_A_UART2S           \
 338                 | SICR_1_USB_B_UART2RTS         \
 339                 | SICR_1_FEC1_FEC1              \
 340                 | SICR_1_FEC2_FEC2              \
 341                 )
 342
 343 /* 0x00080400 SICR_2 */
 344 #define CONFIG_SYS_SICRH (0                     \
 345                 | SICR_2_FEC3_FEC3              \
 346                 | SICR_2_HDLC1_A_HDLC1          \
 347                 | SICR_2_ELBC_A_LA              \
 348                 | SICR_2_ELBC_B_LCLK            \
 349                 | SICR_2_HDLC2_A_HDLC2          \
 350                 | SICR_2_USB_D_GPIO             \
 351                 | SICR_2_PCI_PCI                \
 352                 | SICR_2_HDLC1_B_HDLC1          \
 353                 | SICR_2_HDLC1_C_HDLC1          \
 354                 | SICR_2_HDLC2_B_GPIO           \
 355                 | SICR_2_HDLC2_C_HDLC2          \
 356                 | SICR_2_QUIESCE_B              \
 357                 )
 358
 359 /* GPR_1 */
 360 #define CONFIG_SYS_GPR1  0x50008060
 361
 362 #define CONFIG_SYS_GP1DIR 0x00000000
 363 #define CONFIG_SYS_GP1ODR 0x00000000
 364 #define CONFIG_SYS_GP2DIR 0xFF000000
 365 #define CONFIG_SYS_GP2ODR 0x00000000
 366
 367 #define CONFIG_SYS_DDRCDR (\
 368         DDRCDR_EN | \
 369         DDRCDR_PZ_MAXZ | \
 370         DDRCDR_NZ_MAXZ | \
 371         DDRCDR_M_ODR)
 372
 373 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000007f
 374 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
 375                                          SDRAM_CFG_32_BE | \
 376                                          SDRAM_CFG_SREN | \
 377                                          SDRAM_CFG_HSE)
 378
 379 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
 380 #define CONFIG_SYS_DDR_CLK_CNTL         (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 381 #define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
 382                                  (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
 383
 384 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN | CSCONFIG_AP | \
 385                                          CSCONFIG_ODT_RD_NEVER | \
 386                                          CSCONFIG_ODT_WR_ONLY_CURRENT | \
 387                                          CSCONFIG_ROW_BIT_13 | \
 388                                          CSCONFIG_COL_BIT_10)
 389
 390 #define CONFIG_SYS_DDR_MODE     0x47860242
 391 #define CONFIG_SYS_DDR_MODE2    0x8080c000
 392
 393 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
 394                                  (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
 395                                  (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
 396                                  (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
 397                                  (0 << TIMING_CFG0_WWT_SHIFT) | \
 398                                  (0 << TIMING_CFG0_RRT_SHIFT) | \
 399                                  (0 << TIMING_CFG0_WRT_SHIFT) | \
 400                                  (0 << TIMING_CFG0_RWT_SHIFT))
 401
 402 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
 403                                  (2 << TIMING_CFG1_WRTORD_SHIFT) | \
 404                                  (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
 405                                  (3 << TIMING_CFG1_WRREC_SHIFT) | \
 406                                  (7 << TIMING_CFG1_REFREC_SHIFT) | \
 407                                  (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
 408                                  (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
 409                                  (3 << TIMING_CFG1_PRETOACT_SHIFT))
 410
 411 #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
 412                                  (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
 413                                  (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
 414                                  (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
 415                                  (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
 416                                  (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
 417                                  (5 << TIMING_CFG2_CPO_SHIFT))
 418
 419 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 420
 421 #define CONFIG_SYS_KMBEC_FPGA_BASE      0xE8000000
 422 #define CONFIG_SYS_KMBEC_FPGA_SIZE      128
 423
 424 /* EEprom support */
 425 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 426
 427 /*
 428  * Local Bus Configuration & Clock Setup
 429  */
 430 #define CONFIG_SYS_LCRR_DBYP    0x80000000
 431 #define CONFIG_SYS_LCRR_EADC    0x00010000
 432 #define CONFIG_SYS_LCRR_CLKDIV  0x00000002
 433
 434 #define CONFIG_SYS_LBC_LBCR     0x00000000
 435
 436 /*
 437  * MMU Setup
 438  */
 439 #define CONFIG_SYS_IBAT7L       (0)
 440 #define CONFIG_SYS_IBAT7U       (0)
 441 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 442 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 443
 444 #define CONFIG_SYS_APP1_BASE            0xA0000000
 445 #define CONFIG_SYS_APP1_SIZE            256 /* Megabytes */
 446 #define CONFIG_SYS_APP2_BASE            0xB0000000
 447 #define CONFIG_SYS_APP2_SIZE            256 /* Megabytes */
 448
 449 /* EEprom support */
 450 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 451
 452 /*
 453  * Init Local Bus Memory Controller:
 454  *
 455  * Bank Bus     Machine PortSz  Size  Device
 456  * ---- ---     ------- ------  -----  ------
 457  *  2   Local   UPMA    16 bit  256MB APP1
 458  *  3   Local   GPCM    16 bit  256MB APP2
 459  *
 460  */
 461
 462 /*
 463  * APP1 on the local bus CS2
 464  */
 465 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_APP1_BASE
 466 #define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_256MB)
 467
 468 #define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_APP1_BASE | \
 469                                  BR_PS_16 | \
 470                                  BR_MS_UPMA | \
 471                                  BR_V)
 472 #define CONFIG_SYS_OR2_PRELIM   (MEG_TO_AM(CONFIG_SYS_APP1_SIZE))
 473
 474 #define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_APP2_BASE | \
 475                                  BR_PS_16 | \
 476                                  BR_V)
 477
 478 #define CONFIG_SYS_OR3_PRELIM   (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
 479                                  OR_GPCM_CSNT | \
 480                                  OR_GPCM_ACS_DIV4 | \
 481                                  OR_GPCM_SCY_3 | \
 482                                  OR_GPCM_TRLX_SET)
 483
 484 #define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \
 485                          0x0000c000 | \
 486                          MxMR_WLFx_2X)
 487
 488 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_APP2_BASE
 489 #define CONFIG_SYS_LBLAWAR3_PRELIM      (LBLAWAR_EN | LBLAWAR_256MB)
 490
 491 /*
 492  * MMU Setup
 493  */
 494 /* APP1:  icache cacheable, but dcache-inhibit and guarded */
 495 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \
 496                                  BATL_MEMCOHERENCE)
 497 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_APP1_BASE | BATU_BL_256M | \
 498                                  BATU_VS | BATU_VP)
 499 #define CONFIG_SYS_DBAT5L       (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \
 500                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 501 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 502 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \
 503                                  BATL_MEMCOHERENCE)
 504 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_APP2_BASE | BATU_BL_256M | \
 505                                  BATU_VS | BATU_VP)
 506 #define CONFIG_SYS_DBAT6L       (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \
 507                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 508 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 509
 510 /*
 511  * QE UEC ethernet configuration
 512  */
 513 #define CONFIG_MV88E6352_SWITCH
 514 #define CONFIG_KM_MVEXTSW_ADDR          0x10
 515
 516 /* ethernet port connected to simple switch 88e6122 (UEC0) */
 517 #define CONFIG_UEC_ETH1
 518 #define CONFIG_SYS_UEC1_UCC_NUM         0       /* UCC1 */
 519 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK9
 520 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK10
 521
 522 #define CONFIG_FIXED_PHY                0xFFFFFFFF
 523 #define CONFIG_SYS_FIXED_PHY_ADDR       0x1E    /* unused address */
 524 #define CONFIG_SYS_FIXED_PHY_PORT(devnum, speed, duplex) \
 525                 {devnum, speed, duplex}
 526 #define CONFIG_SYS_FIXED_PHY_PORTS \
 527                 CONFIG_SYS_FIXED_PHY_PORT("UEC0", SPEED_100, DUPLEX_FULL)
 528
 529 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 530 #define CONFIG_SYS_UEC1_PHY_ADDR        CONFIG_SYS_FIXED_PHY_ADDR
 531 #define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
 532 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 533
 534 /* ethernet port connected to piggy (UEC2) */
 535 #define CONFIG_HAS_ETH1
 536 #define CONFIG_UEC_ETH2
 537 #define CONFIG_SYS_UEC2_UCC_NUM         2       /* UCC3 */
 538 #define CONFIG_SYS_UEC2_RX_CLK          QE_CLK_NONE /* not used in RMII Mode */
 539 #define CONFIG_SYS_UEC2_TX_CLK          QE_CLK12
 540 #define CONFIG_SYS_UEC2_ETH_TYPE        FAST_ETH
 541 #define CONFIG_SYS_UEC2_PHY_ADDR        0
 542 #define CONFIG_SYS_UEC2_INTERFACE_TYPE  PHY_INTERFACE_MODE_RMII
 543 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
 544
 545 #endif /* __CONFIG_H */