include/configs/kmvect1.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   4  *                    Dave Liu <daveliu@freescale.com>
   5  *
   6  * Copyright (C) 2007 Logic Product Development, Inc.
   7  *                    Peter Barada <peterb@logicpd.com>
   8  *
   9  * Copyright (C) 2007 MontaVista Software, Inc.
  10  *                    Anton Vorontsov <avorontsov@ru.mvista.com>
  11  *
  12  * (C) Copyright 2010
  13  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  14  */
  15
  16 #ifndef __CONFIG_H
  17 #define __CONFIG_H
  18
  19 /*
  20  * High Level Configuration Options
  21  */
  22
  23 /* This needs to be set prior to including km83xx-common.h */
  24
  25 #define CONFIG_HOSTNAME         "kmvect1"
  26 #define CONFIG_KM_BOARD_NAME   "kmvect1"
  27 /* at end of uboot partition, before env */
  28 #define CONFIG_SYS_QE_FW_ADDR   0xF00B0000
  29 /* include common defines/options for all 8309 Keymile boards */
  30 #include "km8309-common.h"
  31
  32 #define CONFIG_SYS_APP1_BASE            0xA0000000
  33 #define CONFIG_SYS_APP1_SIZE            256 /* Megabytes */
  34 #define CONFIG_SYS_APP2_BASE            0xB0000000
  35 #define CONFIG_SYS_APP2_SIZE            256 /* Megabytes */
  36
  37 /* EEprom support */
  38 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
  39
  40 /*
  41  * Init Local Bus Memory Controller:
  42  *
  43  * Bank Bus     Machine PortSz  Size  Device
  44  * ---- ---     ------- ------  -----  ------
  45  *  2   Local   UPMA    16 bit  256MB APP1
  46  *  3   Local   GPCM    16 bit  256MB APP2
  47  *
  48  */
  49
  50 /*
  51  * APP1 on the local bus CS2
  52  */
  53 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_APP1_BASE
  54 #define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_256MB)
  55
  56 #define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_APP1_BASE | \
  57                                  BR_PS_16 | \
  58                                  BR_MS_UPMA | \
  59                                  BR_V)
  60 #define CONFIG_SYS_OR2_PRELIM   (MEG_TO_AM(CONFIG_SYS_APP1_SIZE))
  61
  62 #define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_APP2_BASE | \
  63                                  BR_PS_16 | \
  64                                  BR_V)
  65
  66 #define CONFIG_SYS_OR3_PRELIM   (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
  67                                  OR_GPCM_CSNT | \
  68                                  OR_GPCM_ACS_DIV4 | \
  69                                  OR_GPCM_SCY_3 | \
  70                                  OR_GPCM_TRLX_SET)
  71
  72 #define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \
  73                          0x0000c000 | \
  74                          MxMR_WLFx_2X)
  75
  76 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_APP2_BASE
  77 #define CONFIG_SYS_LBLAWAR3_PRELIM      (LBLAWAR_EN | LBLAWAR_256MB)
  78
  79 /*
  80  * MMU Setup
  81  */
  82 /* APP1:  icache cacheable, but dcache-inhibit and guarded */
  83 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \
  84                                  BATL_MEMCOHERENCE)
  85 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_APP1_BASE | BATU_BL_256M | \
  86                                  BATU_VS | BATU_VP)
  87 #define CONFIG_SYS_DBAT5L       (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \
  88                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
  89 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
  90 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \
  91                                  BATL_MEMCOHERENCE)
  92 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_APP2_BASE | BATU_BL_256M | \
  93                                  BATU_VS | BATU_VP)
  94 #define CONFIG_SYS_DBAT6L       (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \
  95                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
  96 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
  97
  98 /*
  99  * QE UEC ethernet configuration
 100  */
 101 #define CONFIG_MV88E6352_SWITCH
 102 #define CONFIG_KM_MVEXTSW_ADDR          0x10
 103
 104 /* ethernet port connected to simple switch 88e6122 (UEC0) */
 105 #define CONFIG_UEC_ETH1
 106 #define CONFIG_SYS_UEC1_UCC_NUM         0       /* UCC1 */
 107 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK9
 108 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK10
 109
 110 #define CONFIG_FIXED_PHY                0xFFFFFFFF
 111 #define CONFIG_SYS_FIXED_PHY_ADDR       0x1E    /* unused address */
 112 #define CONFIG_SYS_FIXED_PHY_PORT(devnum, speed, duplex) \
 113                 {devnum, speed, duplex}
 114 #define CONFIG_SYS_FIXED_PHY_PORTS \
 115                 CONFIG_SYS_FIXED_PHY_PORT("UEC0", SPEED_100, DUPLEX_FULL)
 116
 117 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 118 #define CONFIG_SYS_UEC1_PHY_ADDR        CONFIG_SYS_FIXED_PHY_ADDR
 119 #define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
 120 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 121
 122 /* ethernet port connected to piggy (UEC2) */
 123 #define CONFIG_HAS_ETH1
 124 #define CONFIG_UEC_ETH2
 125 #define CONFIG_SYS_UEC2_UCC_NUM         2       /* UCC3 */
 126 #define CONFIG_SYS_UEC2_RX_CLK          QE_CLK_NONE /* not used in RMII Mode */
 127 #define CONFIG_SYS_UEC2_TX_CLK          QE_CLK12
 128 #define CONFIG_SYS_UEC2_ETH_TYPE        FAST_ETH
 129 #define CONFIG_SYS_UEC2_PHY_ADDR        0
 130 #define CONFIG_SYS_UEC2_INTERFACE_TYPE  PHY_INTERFACE_MODE_RMII
 131 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
 132
 133 #endif /* __CONFIG_H */