include/configs/kmvect1.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   4  *                    Dave Liu <daveliu@freescale.com>
   5  *
   6  * Copyright (C) 2007 Logic Product Development, Inc.
   7  *                    Peter Barada <peterb@logicpd.com>
   8  *
   9  * Copyright (C) 2007 MontaVista Software, Inc.
  10  *                    Anton Vorontsov <avorontsov@ru.mvista.com>
  11  *
  12  * (C) Copyright 2010
  13  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  14  */
  15
  16 #ifndef __CONFIG_H
  17 #define __CONFIG_H
  18
  19 /*
  20  * High Level Configuration Options
  21  */
  22
  23 #define CONFIG_HOSTNAME         "kmvect1"
  24 #define CONFIG_KM_BOARD_NAME   "kmvect1"
  25 /* at end of uboot partition, before env */
  26 #define CONFIG_SYS_QE_FW_ADDR   0xF00B0000
  27
  28 /*
  29  * High Level Configuration Options
  30  */
  31 #define CONFIG_E300             1       /* E300 family */
  32 #define CONFIG_QE               1       /* Has QE */
  33
  34 #define CONFIG_KM_DEF_ARCH      "arch=ppc_82xx\0"
  35
  36 /* include common defines/options for all Keymile boards */
  37 #include "km/keymile-common.h"
  38 #include "km/km-powerpc.h"
  39
  40 /*
  41  * System Clock Setup
  42  */
  43 #define CONFIG_83XX_CLKIN               66000000
  44 #define CONFIG_SYS_CLK_FREQ             66000000
  45 #define CONFIG_83XX_PCICLK              66000000
  46
  47 /*
  48  * DDR Setup
  49  */
  50 #define CONFIG_SYS_SDRAM_BASE           0x00000000 /* DDR is system memory */
  51 #define CONFIG_SYS_SDRAM_BASE2  (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
  52
  53 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN | \
  54                                         DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  55
  56 #define CFG_83XX_DDR_USES_CS0
  57
  58 /*
  59  * Manually set up DDR parameters
  60  */
  61 #define CONFIG_DDR_II
  62 #define CONFIG_SYS_DDR_SIZE             2048 /* MB */
  63
  64 /*
  65  * The reserved memory
  66  */
  67 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  68 #define CONFIG_SYS_FLASH_BASE           0xF0000000
  69
  70 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  71 #define CONFIG_SYS_RAMBOOT
  72 #endif
  73
  74 /* Reserve 768 kB for Mon */
  75 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
  76
  77 /*
  78  * Initial RAM Base Address Setup
  79  */
  80 #define CONFIG_SYS_INIT_RAM_LOCK
  81 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
  82 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* End of used area in RAM */
  83 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
  84                                                 GENERATED_GBL_DATA_SIZE)
  85
  86 /*
  87  * Init Local Bus Memory Controller:
  88  *
  89  * Bank Bus     Machine PortSz  Size  Device
  90  * ---- ---     ------- ------  -----  ------
  91  *  0   Local   GPCM    16 bit  256MB FLASH
  92  *  1   Local   GPCM     8 bit  128MB GPIO/PIGGY
  93  *
  94  */
  95 /*
  96  * FLASH on the Local Bus
  97  */
  98 #define CONFIG_SYS_FLASH_SIZE           256 /* max FLASH size is 256M */
  99
 100
 101 #define CONFIG_SYS_MAX_FLASH_BANKS      1   /* max num of flash banks   */
 102 #define CONFIG_SYS_MAX_FLASH_SECT       512 /* max num of sects on one chip */
 103 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
 104
 105 /*
 106  * PRIO1/PIGGY on the local bus CS1
 107  */
 108
 109
 110 /*
 111  * Serial Port
 112  */
 113 #define CONFIG_SYS_NS16550_SERIAL
 114 #define CONFIG_SYS_NS16550_REG_SIZE     1
 115 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 116
 117 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 118 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 119
 120 /*
 121  * QE UEC ethernet configuration
 122  */
 123 #define CONFIG_UEC_ETH
 124 #define CONFIG_ETHPRIME         "UEC0"
 125
 126 #ifdef CONFIG_UEC_ETH1
 127 #define CONFIG_SYS_UEC1_UCC_NUM 3       /* UCC4 */
 128 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK_NONE /* not used in RMII Mode */
 129 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK17
 130 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 131 #define CONFIG_SYS_UEC1_PHY_ADDR        0
 132 #define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_RMII
 133 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 134 #endif
 135
 136 /*
 137  * Environment
 138  */
 139
 140 #ifndef CONFIG_SYS_RAMBOOT
 141 #ifndef CONFIG_ENV_ADDR
 142 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 143                                         CONFIG_SYS_MONITOR_LEN)
 144 #endif
 145 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 146 #ifndef CONFIG_ENV_OFFSET
 147 #define CONFIG_ENV_OFFSET       (CONFIG_SYS_MONITOR_LEN)
 148 #endif
 149
 150 /* Address and size of Redundant Environment Sector     */
 151 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + \
 152                                                 CONFIG_ENV_SECT_SIZE)
 153 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 154
 155 #else /* CFG_SYS_RAMBOOT */
 156 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 157 #define CONFIG_ENV_SIZE         0x2000
 158 #endif /* CFG_SYS_RAMBOOT */
 159
 160 /* I2C */
 161 #define CONFIG_SYS_I2C
 162 #define CONFIG_SYS_NUM_I2C_BUSES        4
 163 #define CONFIG_SYS_I2C_MAX_HOPS         1
 164 #define CONFIG_SYS_I2C_FSL
 165 #define CONFIG_SYS_FSL_I2C_SPEED        200000
 166 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 167 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 168 #define CONFIG_SYS_I2C_OFFSET           0x3000
 169 #define CONFIG_SYS_FSL_I2C2_SPEED       200000
 170 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 171 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 172 #define CONFIG_SYS_I2C_BUSES    {{0, {I2C_NULL_HOP} }, \
 173                 {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
 174                 {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
 175                 {1, {I2C_NULL_HOP} } }
 176
 177 #define CONFIG_KM_IVM_BUS               2       /* I2C2 (Mux-Port 1)*/
 178
 179 #if defined(CONFIG_CMD_NAND)
 180 #define CONFIG_NAND_KMETER1
 181 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 182 #define CONFIG_SYS_NAND_BASE            CONFIG_SYS_KMBEC_FPGA_BASE
 183 #endif
 184
 185 /*
 186  * For booting Linux, the board info and command line data
 187  * have to be in the first 8 MB of memory, since this is
 188  * the maximum mapped by the Linux kernel during initialization.
 189  */
 190 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)
 191
 192 /*
 193  * Internal Definitions
 194  */
 195 #define BOOTFLASH_START 0xF0000000
 196
 197 #define CONFIG_KM_CONSOLE_TTY   "ttyS0"
 198
 199 /*
 200  * Environment Configuration
 201  */
 202 #define CONFIG_ENV_OVERWRITE
 203 #ifndef CONFIG_KM_DEF_ENV               /* if not set by keymile-common.h */
 204 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
 205 #endif
 206
 207 #ifndef CONFIG_KM_DEF_ARCH
 208 #define CONFIG_KM_DEF_ARCH      "arch=ppc_82xx\0"
 209 #endif
 210
 211 #define CONFIG_EXTRA_ENV_SETTINGS \
 212         CONFIG_KM_DEF_ENV                                               \
 213         CONFIG_KM_DEF_ARCH                                              \
 214         "newenv="                                                       \
 215                 "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && "  \
 216                 "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0"         \
 217         "unlock=yes\0"                                                  \
 218         ""
 219
 220 #if defined(CONFIG_UEC_ETH)
 221 #define CONFIG_HAS_ETH0
 222 #endif
 223
 224 /* QE microcode/firmware address */
 225 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 226 /* between the u-boot partition and env */
 227 #ifndef CONFIG_SYS_QE_FW_ADDR
 228 #define CONFIG_SYS_QE_FW_ADDR   0xF00C0000
 229 #endif
 230
 231 /*
 232  * System IO Config
 233  */
 234 /* 0x14000180 SICR_1 */
 235 #define CONFIG_SYS_SICRL (0                     \
 236                 | SICR_1_UART1_UART1RTS         \
 237                 | SICR_1_I2C_CKSTOP             \
 238                 | SICR_1_IRQ_A_IRQ              \
 239                 | SICR_1_IRQ_B_IRQ              \
 240                 | SICR_1_GPIO_A_GPIO            \
 241                 | SICR_1_GPIO_B_GPIO            \
 242                 | SICR_1_GPIO_C_GPIO            \
 243                 | SICR_1_GPIO_D_GPIO            \
 244                 | SICR_1_GPIO_E_GPIO            \
 245                 | SICR_1_GPIO_F_GPIO            \
 246                 | SICR_1_USB_A_UART2S           \
 247                 | SICR_1_USB_B_UART2RTS         \
 248                 | SICR_1_FEC1_FEC1              \
 249                 | SICR_1_FEC2_FEC2              \
 250                 )
 251
 252 /* 0x00080400 SICR_2 */
 253 #define CONFIG_SYS_SICRH (0                     \
 254                 | SICR_2_FEC3_FEC3              \
 255                 | SICR_2_HDLC1_A_HDLC1          \
 256                 | SICR_2_ELBC_A_LA              \
 257                 | SICR_2_ELBC_B_LCLK            \
 258                 | SICR_2_HDLC2_A_HDLC2          \
 259                 | SICR_2_USB_D_GPIO             \
 260                 | SICR_2_PCI_PCI                \
 261                 | SICR_2_HDLC1_B_HDLC1          \
 262                 | SICR_2_HDLC1_C_HDLC1          \
 263                 | SICR_2_HDLC2_B_GPIO           \
 264                 | SICR_2_HDLC2_C_HDLC2          \
 265                 | SICR_2_QUIESCE_B              \
 266                 )
 267
 268 /* GPR_1 */
 269 #define CONFIG_SYS_GPR1  0x50008060
 270
 271 #define CONFIG_SYS_GP1DIR 0x00000000
 272 #define CONFIG_SYS_GP1ODR 0x00000000
 273 #define CONFIG_SYS_GP2DIR 0xFF000000
 274 #define CONFIG_SYS_GP2ODR 0x00000000
 275
 276 #define CONFIG_SYS_DDRCDR (\
 277         DDRCDR_EN | \
 278         DDRCDR_PZ_MAXZ | \
 279         DDRCDR_NZ_MAXZ | \
 280         DDRCDR_M_ODR)
 281
 282 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000007f
 283 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
 284                                          SDRAM_CFG_32_BE | \
 285                                          SDRAM_CFG_SREN | \
 286                                          SDRAM_CFG_HSE)
 287
 288 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
 289 #define CONFIG_SYS_DDR_CLK_CNTL         (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 290 #define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
 291                                  (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
 292
 293 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN | CSCONFIG_AP | \
 294                                          CSCONFIG_ODT_RD_NEVER | \
 295                                          CSCONFIG_ODT_WR_ONLY_CURRENT | \
 296                                          CSCONFIG_ROW_BIT_13 | \
 297                                          CSCONFIG_COL_BIT_10)
 298
 299 #define CONFIG_SYS_DDR_MODE     0x47860242
 300 #define CONFIG_SYS_DDR_MODE2    0x8080c000
 301
 302 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
 303                                  (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
 304                                  (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
 305                                  (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
 306                                  (0 << TIMING_CFG0_WWT_SHIFT) | \
 307                                  (0 << TIMING_CFG0_RRT_SHIFT) | \
 308                                  (0 << TIMING_CFG0_WRT_SHIFT) | \
 309                                  (0 << TIMING_CFG0_RWT_SHIFT))
 310
 311 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
 312                                  (2 << TIMING_CFG1_WRTORD_SHIFT) | \
 313                                  (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
 314                                  (3 << TIMING_CFG1_WRREC_SHIFT) | \
 315                                  (7 << TIMING_CFG1_REFREC_SHIFT) | \
 316                                  (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
 317                                  (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
 318                                  (3 << TIMING_CFG1_PRETOACT_SHIFT))
 319
 320 #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
 321                                  (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
 322                                  (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
 323                                  (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
 324                                  (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
 325                                  (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
 326                                  (5 << TIMING_CFG2_CPO_SHIFT))
 327
 328 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 329
 330 #define CONFIG_SYS_KMBEC_FPGA_BASE      0xE8000000
 331 #define CONFIG_SYS_KMBEC_FPGA_SIZE      128
 332
 333 /* EEprom support */
 334 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 335
 336 #define CONFIG_SYS_APP1_BASE            0xA0000000
 337 #define CONFIG_SYS_APP1_SIZE            256 /* Megabytes */
 338 #define CONFIG_SYS_APP2_BASE            0xB0000000
 339 #define CONFIG_SYS_APP2_SIZE            256 /* Megabytes */
 340
 341 /* EEprom support */
 342 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 343
 344 /*
 345  * Init Local Bus Memory Controller:
 346  *
 347  * Bank Bus     Machine PortSz  Size  Device
 348  * ---- ---     ------- ------  -----  ------
 349  *  2   Local   UPMA    16 bit  256MB APP1
 350  *  3   Local   GPCM    16 bit  256MB APP2
 351  *
 352  */
 353
 354
 355
 356 #define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \
 357                          0x0000c000 | \
 358                          MxMR_WLFx_2X)
 359 /*
 360  * QE UEC ethernet configuration
 361  */
 362 #define CONFIG_MV88E6352_SWITCH
 363 #define CONFIG_KM_MVEXTSW_ADDR          0x10
 364
 365 /* ethernet port connected to simple switch 88e6122 (UEC0) */
 366 #define CONFIG_UEC_ETH1
 367 #define CONFIG_SYS_UEC1_UCC_NUM         0       /* UCC1 */
 368 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK9
 369 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK10
 370
 371 #define CONFIG_FIXED_PHY                0xFFFFFFFF
 372 #define CONFIG_SYS_FIXED_PHY_ADDR       0x1E    /* unused address */
 373 #define CONFIG_SYS_FIXED_PHY_PORT(devnum, speed, duplex) \
 374                 {devnum, speed, duplex}
 375 #define CONFIG_SYS_FIXED_PHY_PORTS \
 376                 CONFIG_SYS_FIXED_PHY_PORT("UEC0", SPEED_100, DUPLEX_FULL)
 377
 378 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 379 #define CONFIG_SYS_UEC1_PHY_ADDR        CONFIG_SYS_FIXED_PHY_ADDR
 380 #define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
 381 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 382
 383 /* ethernet port connected to piggy (UEC2) */
 384 #define CONFIG_HAS_ETH1
 385 #define CONFIG_UEC_ETH2
 386 #define CONFIG_SYS_UEC2_UCC_NUM         2       /* UCC3 */
 387 #define CONFIG_SYS_UEC2_RX_CLK          QE_CLK_NONE /* not used in RMII Mode */
 388 #define CONFIG_SYS_UEC2_TX_CLK          QE_CLK12
 389 #define CONFIG_SYS_UEC2_ETH_TYPE        FAST_ETH
 390 #define CONFIG_SYS_UEC2_PHY_ADDR        0
 391 #define CONFIG_SYS_UEC2_INTERFACE_TYPE  PHY_INTERFACE_MODE_RMII
 392 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
 393
 394 #endif /* __CONFIG_H */