include/configs/kmtegr1.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   4  *                    Dave Liu <daveliu@freescale.com>
   5  *
   6  * Copyright (C) 2007 Logic Product Development, Inc.
   7  *                    Peter Barada <peterb@logicpd.com>
   8  *
   9  * Copyright (C) 2007 MontaVista Software, Inc.
  10  *                    Anton Vorontsov <avorontsov@ru.mvista.com>
  11  *
  12  * (C) Copyright 2010
  13  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  14  */
  15
  16 #ifndef __CONFIG_H
  17 #define __CONFIG_H
  18
  19 /*
  20  * High Level Configuration Options
  21  */
  22
  23 #define CONFIG_HOSTNAME   "kmtegr1"
  24 #define CONFIG_KM_BOARD_NAME   "kmtegr1"
  25 #define CONFIG_KM_UBI_PARTITION_NAME_BOOT       "ubi0"
  26 #define CONFIG_KM_UBI_PARTITION_NAME_APP        "ubi1"
  27
  28 #define CONFIG_ENV_ADDR         0xF0100000
  29 #define CONFIG_ENV_OFFSET       0x100000
  30
  31 #define CONFIG_NAND_ECC_BCH
  32 #define CONFIG_NAND_KMETER1
  33 #define CONFIG_SYS_MAX_NAND_DEVICE              1
  34 #define NAND_MAX_CHIPS                          1
  35
  36 /*
  37  * High Level Configuration Options
  38  */
  39 #define CONFIG_E300             1       /* E300 family */
  40 #define CONFIG_QE               1       /* Has QE */
  41
  42 #define CONFIG_KM_DEF_ARCH      "arch=ppc_82xx\0"
  43
  44 /* include common defines/options for all Keymile boards */
  45 #include "km/keymile-common.h"
  46 #include "km/km-powerpc.h"
  47
  48 /*
  49  * System Clock Setup
  50  */
  51 #define CONFIG_83XX_CLKIN               66000000
  52 #define CONFIG_SYS_CLK_FREQ             66000000
  53 #define CONFIG_83XX_PCICLK              66000000
  54
  55 /*
  56  * IMMR new address
  57  */
  58 #define CONFIG_SYS_IMMR         0xE0000000
  59
  60 /*
  61  * Bus Arbitration Configuration Register (ACR)
  62  */
  63 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* pipeline depth 4 transactions */
  64 #define CONFIG_SYS_ACR_RPTCNT   3       /* 4 consecutive transactions */
  65 #define CONFIG_SYS_ACR_APARK    0       /* park bus to master (below) */
  66 #define CONFIG_SYS_ACR_PARKM    3       /* parking master = QuiccEngine */
  67
  68 /*
  69  * DDR Setup
  70  */
  71 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
  72 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  73 #define CONFIG_SYS_SDRAM_BASE2  (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
  74
  75 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  76 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN | \
  77                                         DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  78
  79 #define CFG_83XX_DDR_USES_CS0
  80
  81 /*
  82  * Manually set up DDR parameters
  83  */
  84 #define CONFIG_DDR_II
  85 #define CONFIG_SYS_DDR_SIZE             2048 /* MB */
  86
  87 /*
  88  * The reserved memory
  89  */
  90 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  91 #define CONFIG_SYS_FLASH_BASE           0xF0000000
  92
  93 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  94 #define CONFIG_SYS_RAMBOOT
  95 #endif
  96
  97 /* Reserve 768 kB for Mon */
  98 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
  99
 100 /*
 101  * Initial RAM Base Address Setup
 102  */
 103 #define CONFIG_SYS_INIT_RAM_LOCK
 104 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 105 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* End of used area in RAM */
 106 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 107                                                 GENERATED_GBL_DATA_SIZE)
 108
 109 /*
 110  * Init Local Bus Memory Controller:
 111  *
 112  * Bank Bus     Machine PortSz  Size  Device
 113  * ---- ---     ------- ------  -----  ------
 114  *  0   Local   GPCM    16 bit  256MB FLASH
 115  *  1   Local   GPCM     8 bit  128MB GPIO/PIGGY
 116  *
 117  */
 118 /*
 119  * FLASH on the Local Bus
 120  */
 121 #define CONFIG_SYS_FLASH_SIZE           256 /* max FLASH size is 256M */
 122
 123 /* FLASH */
 124 #define CONFIG_SYS_BR0_PRELIM   (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V)
 125 #define CONFIG_SYS_OR0_PRELIM   (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 126
 127 #define CONFIG_SYS_MAX_FLASH_BANKS      1   /* max num of flash banks   */
 128 #define CONFIG_SYS_MAX_FLASH_SECT       512 /* max num of sects on one chip */
 129 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
 130
 131 /*
 132  * PRIO1/PIGGY on the local bus CS1
 133  */
 134
 135 /* KMBEC_FPGA */
 136 #define CONFIG_SYS_BR1_PRELIM   (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V)
 137 #define CONFIG_SYS_OR1_PRELIM   (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 138
 139 /*
 140  * Serial Port
 141  */
 142 #define CONFIG_SYS_NS16550_SERIAL
 143 #define CONFIG_SYS_NS16550_REG_SIZE     1
 144 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 145
 146 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 147 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 148
 149 /*
 150  * QE UEC ethernet configuration
 151  */
 152 #define CONFIG_UEC_ETH
 153 #define CONFIG_ETHPRIME         "UEC0"
 154
 155 #ifdef CONFIG_UEC_ETH1
 156 #define CONFIG_SYS_UEC1_UCC_NUM 3       /* UCC4 */
 157 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK_NONE /* not used in RMII Mode */
 158 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK17
 159 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 160 #define CONFIG_SYS_UEC1_PHY_ADDR        0
 161 #define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_RMII
 162 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 163 #endif
 164
 165 /*
 166  * Environment
 167  */
 168
 169 #ifndef CONFIG_SYS_RAMBOOT
 170 #ifndef CONFIG_ENV_ADDR
 171 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 172                                         CONFIG_SYS_MONITOR_LEN)
 173 #endif
 174 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 175 #ifndef CONFIG_ENV_OFFSET
 176 #define CONFIG_ENV_OFFSET       (CONFIG_SYS_MONITOR_LEN)
 177 #endif
 178
 179 /* Address and size of Redundant Environment Sector     */
 180 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + \
 181                                                 CONFIG_ENV_SECT_SIZE)
 182 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 183
 184 #else /* CFG_SYS_RAMBOOT */
 185 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 186 #define CONFIG_ENV_SIZE         0x2000
 187 #endif /* CFG_SYS_RAMBOOT */
 188
 189 /* I2C */
 190 #define CONFIG_SYS_I2C
 191 #define CONFIG_SYS_NUM_I2C_BUSES        4
 192 #define CONFIG_SYS_I2C_MAX_HOPS         1
 193 #define CONFIG_SYS_I2C_FSL
 194 #define CONFIG_SYS_FSL_I2C_SPEED        200000
 195 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 196 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 197 #define CONFIG_SYS_I2C_OFFSET           0x3000
 198 #define CONFIG_SYS_FSL_I2C2_SPEED       200000
 199 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 200 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 201 #define CONFIG_SYS_I2C_BUSES    {{0, {I2C_NULL_HOP} }, \
 202                 {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
 203                 {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
 204                 {1, {I2C_NULL_HOP} } }
 205
 206 #define CONFIG_KM_IVM_BUS               2       /* I2C2 (Mux-Port 1)*/
 207
 208 #if defined(CONFIG_CMD_NAND)
 209 #define CONFIG_NAND_KMETER1
 210 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 211 #define CONFIG_SYS_NAND_BASE            CONFIG_SYS_KMBEC_FPGA_BASE
 212 #endif
 213
 214 /*
 215  * For booting Linux, the board info and command line data
 216  * have to be in the first 8 MB of memory, since this is
 217  * the maximum mapped by the Linux kernel during initialization.
 218  */
 219 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)
 220
 221 /*
 222  * Core HID Setup
 223  */
 224 #define CONFIG_SYS_HID0_INIT            0x000000000
 225 #define CONFIG_SYS_HID0_FINAL           (HID0_ENABLE_MACHINE_CHECK | \
 226                                          HID0_ENABLE_INSTRUCTION_CACHE)
 227 #define CONFIG_SYS_HID2                 HID2_HBE
 228
 229 /*
 230  * Internal Definitions
 231  */
 232 #define BOOTFLASH_START 0xF0000000
 233
 234 #define CONFIG_KM_CONSOLE_TTY   "ttyS0"
 235
 236 /*
 237  * Environment Configuration
 238  */
 239 #define CONFIG_ENV_OVERWRITE
 240 #ifndef CONFIG_KM_DEF_ENV               /* if not set by keymile-common.h */
 241 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
 242 #endif
 243
 244 #ifndef CONFIG_KM_DEF_ARCH
 245 #define CONFIG_KM_DEF_ARCH      "arch=ppc_82xx\0"
 246 #endif
 247
 248 #define CONFIG_EXTRA_ENV_SETTINGS \
 249         CONFIG_KM_DEF_ENV                                               \
 250         CONFIG_KM_DEF_ARCH                                              \
 251         "newenv="                                                       \
 252                 "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && "  \
 253                 "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0"         \
 254         "unlock=yes\0"                                                  \
 255         ""
 256
 257 #if defined(CONFIG_UEC_ETH)
 258 #define CONFIG_HAS_ETH0
 259 #endif
 260
 261 /* QE microcode/firmware address */
 262 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 263 /* between the u-boot partition and env */
 264 #ifndef CONFIG_SYS_QE_FW_ADDR
 265 #define CONFIG_SYS_QE_FW_ADDR   0xF00C0000
 266 #endif
 267
 268 /*
 269  * System IO Config
 270  */
 271 /* 0x14000180 SICR_1 */
 272 #define CONFIG_SYS_SICRL (0                     \
 273                 | SICR_1_UART1_UART1RTS         \
 274                 | SICR_1_I2C_CKSTOP             \
 275                 | SICR_1_IRQ_A_IRQ              \
 276                 | SICR_1_IRQ_B_IRQ              \
 277                 | SICR_1_GPIO_A_GPIO            \
 278                 | SICR_1_GPIO_B_GPIO            \
 279                 | SICR_1_GPIO_C_GPIO            \
 280                 | SICR_1_GPIO_D_GPIO            \
 281                 | SICR_1_GPIO_E_GPIO            \
 282                 | SICR_1_GPIO_F_GPIO            \
 283                 | SICR_1_USB_A_UART2S           \
 284                 | SICR_1_USB_B_UART2RTS         \
 285                 | SICR_1_FEC1_FEC1              \
 286                 | SICR_1_FEC2_FEC2              \
 287                 )
 288
 289 /* 0x00080400 SICR_2 */
 290 #define CONFIG_SYS_SICRH (0                     \
 291                 | SICR_2_FEC3_FEC3              \
 292                 | SICR_2_HDLC1_A_HDLC1          \
 293                 | SICR_2_ELBC_A_LA              \
 294                 | SICR_2_ELBC_B_LCLK            \
 295                 | SICR_2_HDLC2_A_HDLC2          \
 296                 | SICR_2_USB_D_GPIO             \
 297                 | SICR_2_PCI_PCI                \
 298                 | SICR_2_HDLC1_B_HDLC1          \
 299                 | SICR_2_HDLC1_C_HDLC1          \
 300                 | SICR_2_HDLC2_B_GPIO           \
 301                 | SICR_2_HDLC2_C_HDLC2          \
 302                 | SICR_2_QUIESCE_B              \
 303                 )
 304
 305 /* GPR_1 */
 306 #define CONFIG_SYS_GPR1  0x50008060
 307
 308 #define CONFIG_SYS_GP1DIR 0x00000000
 309 #define CONFIG_SYS_GP1ODR 0x00000000
 310 #define CONFIG_SYS_GP2DIR 0xFF000000
 311 #define CONFIG_SYS_GP2ODR 0x00000000
 312
 313 #define CONFIG_SYS_DDRCDR (\
 314         DDRCDR_EN | \
 315         DDRCDR_PZ_MAXZ | \
 316         DDRCDR_NZ_MAXZ | \
 317         DDRCDR_M_ODR)
 318
 319 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000007f
 320 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
 321                                          SDRAM_CFG_32_BE | \
 322                                          SDRAM_CFG_SREN | \
 323                                          SDRAM_CFG_HSE)
 324
 325 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
 326 #define CONFIG_SYS_DDR_CLK_CNTL         (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 327 #define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
 328                                  (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
 329
 330 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN | CSCONFIG_AP | \
 331                                          CSCONFIG_ODT_RD_NEVER | \
 332                                          CSCONFIG_ODT_WR_ONLY_CURRENT | \
 333                                          CSCONFIG_ROW_BIT_13 | \
 334                                          CSCONFIG_COL_BIT_10)
 335
 336 #define CONFIG_SYS_DDR_MODE     0x47860242
 337 #define CONFIG_SYS_DDR_MODE2    0x8080c000
 338
 339 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
 340                                  (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
 341                                  (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
 342                                  (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
 343                                  (0 << TIMING_CFG0_WWT_SHIFT) | \
 344                                  (0 << TIMING_CFG0_RRT_SHIFT) | \
 345                                  (0 << TIMING_CFG0_WRT_SHIFT) | \
 346                                  (0 << TIMING_CFG0_RWT_SHIFT))
 347
 348 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
 349                                  (2 << TIMING_CFG1_WRTORD_SHIFT) | \
 350                                  (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
 351                                  (3 << TIMING_CFG1_WRREC_SHIFT) | \
 352                                  (7 << TIMING_CFG1_REFREC_SHIFT) | \
 353                                  (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
 354                                  (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
 355                                  (3 << TIMING_CFG1_PRETOACT_SHIFT))
 356
 357 #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
 358                                  (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
 359                                  (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
 360                                  (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
 361                                  (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
 362                                  (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
 363                                  (5 << TIMING_CFG2_CPO_SHIFT))
 364
 365 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 366
 367 #define CONFIG_SYS_KMBEC_FPGA_BASE      0xE8000000
 368 #define CONFIG_SYS_KMBEC_FPGA_SIZE      128
 369
 370 /* EEprom support */
 371 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 372
 373 /*
 374  * Local Bus Configuration & Clock Setup
 375  */
 376 #define CONFIG_SYS_LCRR_DBYP    0x80000000
 377 #define CONFIG_SYS_LCRR_EADC    0x00010000
 378 #define CONFIG_SYS_LCRR_CLKDIV  0x00000002
 379
 380 #define CONFIG_SYS_LBC_LBCR     0x00000000
 381
 382 /* must be after the include because KMBEC_FPGA is otherwise undefined */
 383 #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
 384
 385 #define CONFIG_SYS_APP1_BASE            0xA0000000
 386 #define CONFIG_SYS_APP1_SIZE            256 /* Megabytes */
 387 #define CONFIG_SYS_APP2_BASE            0xB0000000
 388 #define CONFIG_SYS_APP2_SIZE            256 /* Megabytes */
 389
 390 /* EEprom support */
 391 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 392
 393 /*
 394  * Init Local Bus Memory Controller:
 395  *
 396  * Bank Bus     Machine PortSz  Size  Device
 397  * ---- ---     ------- ------  -----  ------
 398  *  2   Local   UPMA    16 bit  256MB APP1
 399  *  3   Local   GPCM    16 bit  256MB APP2
 400  *
 401  */
 402
 403 /* APP2 */
 404 #define CONFIG_SYS_BR3_PRELIM   (0xB0000000 | BR_PS_16 | BR_MS_GPCM | BR_V)
 405 #define CONFIG_SYS_OR3_PRELIM   (OR_AM_256MB | OR_GPCM_SCY_5 | OR_GPCM_TRLX_CLEAR | OR_GPCM_EHTR_CLEAR)
 406
 407 /* ethernet port connected to piggy (UEC2) */
 408 #define CONFIG_HAS_ETH1
 409 #define CONFIG_UEC_ETH2
 410 #define CONFIG_SYS_UEC2_UCC_NUM         2       /* UCC3 */
 411 #define CONFIG_SYS_UEC2_RX_CLK          QE_CLK_NONE /* not used in RMII Mode */
 412 #define CONFIG_SYS_UEC2_TX_CLK          QE_CLK12
 413 #define CONFIG_SYS_UEC2_ETH_TYPE        FAST_ETH
 414 #define CONFIG_SYS_UEC2_PHY_ADDR        0
 415 #define CONFIG_SYS_UEC2_INTERFACE_TYPE  PHY_INTERFACE_MODE_RMII
 416 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
 417
 418 #endif /* __CONFIG_H */