include/configs/kmtegr1.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   4  *                    Dave Liu <daveliu@freescale.com>
   5  *
   6  * Copyright (C) 2007 Logic Product Development, Inc.
   7  *                    Peter Barada <peterb@logicpd.com>
   8  *
   9  * Copyright (C) 2007 MontaVista Software, Inc.
  10  *                    Anton Vorontsov <avorontsov@ru.mvista.com>
  11  *
  12  * (C) Copyright 2010
  13  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  14  */
  15
  16 #ifndef __CONFIG_H
  17 #define __CONFIG_H
  18
  19 /*
  20  * High Level Configuration Options
  21  */
  22
  23 #define CONFIG_HOSTNAME   "kmtegr1"
  24 #define CONFIG_KM_BOARD_NAME   "kmtegr1"
  25 #define CONFIG_KM_UBI_PARTITION_NAME_BOOT       "ubi0"
  26 #define CONFIG_KM_UBI_PARTITION_NAME_APP        "ubi1"
  27
  28 #define CONFIG_ENV_ADDR         0xF0100000
  29 #define CONFIG_ENV_OFFSET       0x100000
  30
  31 #define CONFIG_NAND_ECC_BCH
  32 #define CONFIG_NAND_KMETER1
  33 #define CONFIG_SYS_MAX_NAND_DEVICE              1
  34 #define NAND_MAX_CHIPS                          1
  35
  36 /*
  37  * High Level Configuration Options
  38  */
  39 #define CONFIG_E300             1       /* E300 family */
  40 #define CONFIG_QE               1       /* Has QE */
  41
  42 #define CONFIG_KM_DEF_ARCH      "arch=ppc_82xx\0"
  43
  44 /* include common defines/options for all Keymile boards */
  45 #include "km/keymile-common.h"
  46 #include "km/km-powerpc.h"
  47
  48 /*
  49  * System Clock Setup
  50  */
  51 #define CONFIG_83XX_CLKIN               66000000
  52 #define CONFIG_SYS_CLK_FREQ             66000000
  53 #define CONFIG_83XX_PCICLK              66000000
  54
  55 /*
  56  * IMMR new address
  57  */
  58 #define CONFIG_SYS_IMMR         0xE0000000
  59
  60 /*
  61  * Bus Arbitration Configuration Register (ACR)
  62  */
  63 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* pipeline depth 4 transactions */
  64 #define CONFIG_SYS_ACR_RPTCNT   3       /* 4 consecutive transactions */
  65 #define CONFIG_SYS_ACR_APARK    0       /* park bus to master (below) */
  66 #define CONFIG_SYS_ACR_PARKM    3       /* parking master = QuiccEngine */
  67
  68 /*
  69  * DDR Setup
  70  */
  71 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
  72 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  73 #define CONFIG_SYS_SDRAM_BASE2  (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
  74
  75 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  76 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN | \
  77                                         DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  78
  79 #define CFG_83XX_DDR_USES_CS0
  80
  81 /*
  82  * Manually set up DDR parameters
  83  */
  84 #define CONFIG_DDR_II
  85 #define CONFIG_SYS_DDR_SIZE             2048 /* MB */
  86
  87 /*
  88  * The reserved memory
  89  */
  90 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  91 #define CONFIG_SYS_FLASH_BASE           0xF0000000
  92
  93 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  94 #define CONFIG_SYS_RAMBOOT
  95 #endif
  96
  97 /* Reserve 768 kB for Mon */
  98 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
  99
 100 /*
 101  * Initial RAM Base Address Setup
 102  */
 103 #define CONFIG_SYS_INIT_RAM_LOCK
 104 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 105 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* End of used area in RAM */
 106 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 107                                                 GENERATED_GBL_DATA_SIZE)
 108
 109 /*
 110  * Init Local Bus Memory Controller:
 111  *
 112  * Bank Bus     Machine PortSz  Size  Device
 113  * ---- ---     ------- ------  -----  ------
 114  *  0   Local   GPCM    16 bit  256MB FLASH
 115  *  1   Local   GPCM     8 bit  128MB GPIO/PIGGY
 116  *
 117  */
 118 /*
 119  * FLASH on the Local Bus
 120  */
 121 #define CONFIG_SYS_FLASH_SIZE           256 /* max FLASH size is 256M */
 122
 123 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE | \
 124                                 BR_PS_16 | /* 16 bit port size */ \
 125                                 BR_MS_GPCM | /* MSEL = GPCM */ \
 126                                 BR_V)
 127
 128 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
 129                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 130                                 OR_GPCM_SCY_5 | \
 131                                 OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 132
 133 #define CONFIG_SYS_MAX_FLASH_BANKS      1   /* max num of flash banks   */
 134 #define CONFIG_SYS_MAX_FLASH_SECT       512 /* max num of sects on one chip */
 135 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
 136
 137 /*
 138  * PRIO1/PIGGY on the local bus CS1
 139  */
 140 /* Window base at flash base */
 141 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_KMBEC_FPGA_BASE | \
 142                                 BR_PS_8 | /* 8 bit port size */ \
 143                                 BR_MS_GPCM | /* MSEL = GPCM */ \
 144                                 BR_V)
 145 #define CONFIG_SYS_OR1_PRELIM   (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \
 146                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 147                                 OR_GPCM_SCY_2 | \
 148                                 OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 149
 150 /*
 151  * Serial Port
 152  */
 153 #define CONFIG_SYS_NS16550_SERIAL
 154 #define CONFIG_SYS_NS16550_REG_SIZE     1
 155 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 156
 157 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 158 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 159
 160 /*
 161  * QE UEC ethernet configuration
 162  */
 163 #define CONFIG_UEC_ETH
 164 #define CONFIG_ETHPRIME         "UEC0"
 165
 166 #ifdef CONFIG_UEC_ETH1
 167 #define CONFIG_SYS_UEC1_UCC_NUM 3       /* UCC4 */
 168 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK_NONE /* not used in RMII Mode */
 169 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK17
 170 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 171 #define CONFIG_SYS_UEC1_PHY_ADDR        0
 172 #define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_RMII
 173 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 174 #endif
 175
 176 /*
 177  * Environment
 178  */
 179
 180 #ifndef CONFIG_SYS_RAMBOOT
 181 #ifndef CONFIG_ENV_ADDR
 182 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 183                                         CONFIG_SYS_MONITOR_LEN)
 184 #endif
 185 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 186 #ifndef CONFIG_ENV_OFFSET
 187 #define CONFIG_ENV_OFFSET       (CONFIG_SYS_MONITOR_LEN)
 188 #endif
 189
 190 /* Address and size of Redundant Environment Sector     */
 191 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + \
 192                                                 CONFIG_ENV_SECT_SIZE)
 193 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 194
 195 #else /* CFG_SYS_RAMBOOT */
 196 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 197 #define CONFIG_ENV_SIZE         0x2000
 198 #endif /* CFG_SYS_RAMBOOT */
 199
 200 /* I2C */
 201 #define CONFIG_SYS_I2C
 202 #define CONFIG_SYS_NUM_I2C_BUSES        4
 203 #define CONFIG_SYS_I2C_MAX_HOPS         1
 204 #define CONFIG_SYS_I2C_FSL
 205 #define CONFIG_SYS_FSL_I2C_SPEED        200000
 206 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 207 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 208 #define CONFIG_SYS_I2C_OFFSET           0x3000
 209 #define CONFIG_SYS_FSL_I2C2_SPEED       200000
 210 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 211 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 212 #define CONFIG_SYS_I2C_BUSES    {{0, {I2C_NULL_HOP} }, \
 213                 {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
 214                 {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
 215                 {1, {I2C_NULL_HOP} } }
 216
 217 #define CONFIG_KM_IVM_BUS               2       /* I2C2 (Mux-Port 1)*/
 218
 219 #if defined(CONFIG_CMD_NAND)
 220 #define CONFIG_NAND_KMETER1
 221 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 222 #define CONFIG_SYS_NAND_BASE            CONFIG_SYS_KMBEC_FPGA_BASE
 223 #endif
 224
 225 /*
 226  * For booting Linux, the board info and command line data
 227  * have to be in the first 8 MB of memory, since this is
 228  * the maximum mapped by the Linux kernel during initialization.
 229  */
 230 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)
 231
 232 /*
 233  * Core HID Setup
 234  */
 235 #define CONFIG_SYS_HID0_INIT            0x000000000
 236 #define CONFIG_SYS_HID0_FINAL           (HID0_ENABLE_MACHINE_CHECK | \
 237                                          HID0_ENABLE_INSTRUCTION_CACHE)
 238 #define CONFIG_SYS_HID2                 HID2_HBE
 239
 240 /*
 241  * Internal Definitions
 242  */
 243 #define BOOTFLASH_START 0xF0000000
 244
 245 #define CONFIG_KM_CONSOLE_TTY   "ttyS0"
 246
 247 /*
 248  * Environment Configuration
 249  */
 250 #define CONFIG_ENV_OVERWRITE
 251 #ifndef CONFIG_KM_DEF_ENV               /* if not set by keymile-common.h */
 252 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
 253 #endif
 254
 255 #ifndef CONFIG_KM_DEF_ARCH
 256 #define CONFIG_KM_DEF_ARCH      "arch=ppc_82xx\0"
 257 #endif
 258
 259 #define CONFIG_EXTRA_ENV_SETTINGS \
 260         CONFIG_KM_DEF_ENV                                               \
 261         CONFIG_KM_DEF_ARCH                                              \
 262         "newenv="                                                       \
 263                 "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && "  \
 264                 "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0"         \
 265         "unlock=yes\0"                                                  \
 266         ""
 267
 268 #if defined(CONFIG_UEC_ETH)
 269 #define CONFIG_HAS_ETH0
 270 #endif
 271
 272 /* QE microcode/firmware address */
 273 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 274 /* between the u-boot partition and env */
 275 #ifndef CONFIG_SYS_QE_FW_ADDR
 276 #define CONFIG_SYS_QE_FW_ADDR   0xF00C0000
 277 #endif
 278
 279 /*
 280  * System IO Config
 281  */
 282 /* 0x14000180 SICR_1 */
 283 #define CONFIG_SYS_SICRL (0                     \
 284                 | SICR_1_UART1_UART1RTS         \
 285                 | SICR_1_I2C_CKSTOP             \
 286                 | SICR_1_IRQ_A_IRQ              \
 287                 | SICR_1_IRQ_B_IRQ              \
 288                 | SICR_1_GPIO_A_GPIO            \
 289                 | SICR_1_GPIO_B_GPIO            \
 290                 | SICR_1_GPIO_C_GPIO            \
 291                 | SICR_1_GPIO_D_GPIO            \
 292                 | SICR_1_GPIO_E_GPIO            \
 293                 | SICR_1_GPIO_F_GPIO            \
 294                 | SICR_1_USB_A_UART2S           \
 295                 | SICR_1_USB_B_UART2RTS         \
 296                 | SICR_1_FEC1_FEC1              \
 297                 | SICR_1_FEC2_FEC2              \
 298                 )
 299
 300 /* 0x00080400 SICR_2 */
 301 #define CONFIG_SYS_SICRH (0                     \
 302                 | SICR_2_FEC3_FEC3              \
 303                 | SICR_2_HDLC1_A_HDLC1          \
 304                 | SICR_2_ELBC_A_LA              \
 305                 | SICR_2_ELBC_B_LCLK            \
 306                 | SICR_2_HDLC2_A_HDLC2          \
 307                 | SICR_2_USB_D_GPIO             \
 308                 | SICR_2_PCI_PCI                \
 309                 | SICR_2_HDLC1_B_HDLC1          \
 310                 | SICR_2_HDLC1_C_HDLC1          \
 311                 | SICR_2_HDLC2_B_GPIO           \
 312                 | SICR_2_HDLC2_C_HDLC2          \
 313                 | SICR_2_QUIESCE_B              \
 314                 )
 315
 316 /* GPR_1 */
 317 #define CONFIG_SYS_GPR1  0x50008060
 318
 319 #define CONFIG_SYS_GP1DIR 0x00000000
 320 #define CONFIG_SYS_GP1ODR 0x00000000
 321 #define CONFIG_SYS_GP2DIR 0xFF000000
 322 #define CONFIG_SYS_GP2ODR 0x00000000
 323
 324 #define CONFIG_SYS_DDRCDR (\
 325         DDRCDR_EN | \
 326         DDRCDR_PZ_MAXZ | \
 327         DDRCDR_NZ_MAXZ | \
 328         DDRCDR_M_ODR)
 329
 330 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000007f
 331 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
 332                                          SDRAM_CFG_32_BE | \
 333                                          SDRAM_CFG_SREN | \
 334                                          SDRAM_CFG_HSE)
 335
 336 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
 337 #define CONFIG_SYS_DDR_CLK_CNTL         (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 338 #define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
 339                                  (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
 340
 341 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN | CSCONFIG_AP | \
 342                                          CSCONFIG_ODT_RD_NEVER | \
 343                                          CSCONFIG_ODT_WR_ONLY_CURRENT | \
 344                                          CSCONFIG_ROW_BIT_13 | \
 345                                          CSCONFIG_COL_BIT_10)
 346
 347 #define CONFIG_SYS_DDR_MODE     0x47860242
 348 #define CONFIG_SYS_DDR_MODE2    0x8080c000
 349
 350 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
 351                                  (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
 352                                  (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
 353                                  (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
 354                                  (0 << TIMING_CFG0_WWT_SHIFT) | \
 355                                  (0 << TIMING_CFG0_RRT_SHIFT) | \
 356                                  (0 << TIMING_CFG0_WRT_SHIFT) | \
 357                                  (0 << TIMING_CFG0_RWT_SHIFT))
 358
 359 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
 360                                  (2 << TIMING_CFG1_WRTORD_SHIFT) | \
 361                                  (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
 362                                  (3 << TIMING_CFG1_WRREC_SHIFT) | \
 363                                  (7 << TIMING_CFG1_REFREC_SHIFT) | \
 364                                  (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
 365                                  (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
 366                                  (3 << TIMING_CFG1_PRETOACT_SHIFT))
 367
 368 #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
 369                                  (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
 370                                  (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
 371                                  (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
 372                                  (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
 373                                  (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
 374                                  (5 << TIMING_CFG2_CPO_SHIFT))
 375
 376 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 377
 378 #define CONFIG_SYS_KMBEC_FPGA_BASE      0xE8000000
 379 #define CONFIG_SYS_KMBEC_FPGA_SIZE      128
 380
 381 /* EEprom support */
 382 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 383
 384 /*
 385  * Local Bus Configuration & Clock Setup
 386  */
 387 #define CONFIG_SYS_LCRR_DBYP    0x80000000
 388 #define CONFIG_SYS_LCRR_EADC    0x00010000
 389 #define CONFIG_SYS_LCRR_CLKDIV  0x00000002
 390
 391 #define CONFIG_SYS_LBC_LBCR     0x00000000
 392
 393 /* must be after the include because KMBEC_FPGA is otherwise undefined */
 394 #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
 395
 396 #define CONFIG_SYS_APP1_BASE            0xA0000000
 397 #define CONFIG_SYS_APP1_SIZE            256 /* Megabytes */
 398 #define CONFIG_SYS_APP2_BASE            0xB0000000
 399 #define CONFIG_SYS_APP2_SIZE            256 /* Megabytes */
 400
 401 /* EEprom support */
 402 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 403
 404 /*
 405  * Init Local Bus Memory Controller:
 406  *
 407  * Bank Bus     Machine PortSz  Size  Device
 408  * ---- ---     ------- ------  -----  ------
 409  *  2   Local   UPMA    16 bit  256MB APP1
 410  *  3   Local   GPCM    16 bit  256MB APP2
 411  *
 412  */
 413
 414 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \
 415                                  BR_PS_16 | \
 416                                  BR_MS_GPCM | \
 417                                  BR_V)
 418
 419 #define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
 420                                  OR_GPCM_SCY_5 | \
 421                                  OR_GPCM_TRLX_CLEAR | \
 422                                  OR_GPCM_EHTR_CLEAR)
 423
 424 /* ethernet port connected to piggy (UEC2) */
 425 #define CONFIG_HAS_ETH1
 426 #define CONFIG_UEC_ETH2
 427 #define CONFIG_SYS_UEC2_UCC_NUM         2       /* UCC3 */
 428 #define CONFIG_SYS_UEC2_RX_CLK          QE_CLK_NONE /* not used in RMII Mode */
 429 #define CONFIG_SYS_UEC2_TX_CLK          QE_CLK12
 430 #define CONFIG_SYS_UEC2_ETH_TYPE        FAST_ETH
 431 #define CONFIG_SYS_UEC2_PHY_ADDR        0
 432 #define CONFIG_SYS_UEC2_INTERFACE_TYPE  PHY_INTERFACE_MODE_RMII
 433 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
 434
 435 #endif /* __CONFIG_H */