include/configs/kmtegr1.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   4  *                    Dave Liu <daveliu@freescale.com>
   5  *
   6  * Copyright (C) 2007 Logic Product Development, Inc.
   7  *                    Peter Barada <peterb@logicpd.com>
   8  *
   9  * Copyright (C) 2007 MontaVista Software, Inc.
  10  *                    Anton Vorontsov <avorontsov@ru.mvista.com>
  11  *
  12  * (C) Copyright 2010
  13  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  14  */
  15
  16 #ifndef __CONFIG_H
  17 #define __CONFIG_H
  18
  19 /*
  20  * High Level Configuration Options
  21  */
  22
  23 #define CONFIG_HOSTNAME   "kmtegr1"
  24 #define CONFIG_KM_BOARD_NAME   "kmtegr1"
  25 #define CONFIG_KM_UBI_PARTITION_NAME_BOOT       "ubi0"
  26 #define CONFIG_KM_UBI_PARTITION_NAME_APP        "ubi1"
  27
  28 #define CONFIG_ENV_ADDR         0xF0100000
  29 #define CONFIG_ENV_OFFSET       0x100000
  30
  31 #define CONFIG_NAND_ECC_BCH
  32 #define CONFIG_NAND_KMETER1
  33 #define CONFIG_SYS_MAX_NAND_DEVICE              1
  34 #define NAND_MAX_CHIPS                          1
  35
  36 /*
  37  * High Level Configuration Options
  38  */
  39 #define CONFIG_E300             1       /* E300 family */
  40 #define CONFIG_QE               1       /* Has QE */
  41
  42 #define CONFIG_KM_DEF_ARCH      "arch=ppc_82xx\0"
  43
  44 /* include common defines/options for all Keymile boards */
  45 #include "km/keymile-common.h"
  46 #include "km/km-powerpc.h"
  47
  48 /*
  49  * System Clock Setup
  50  */
  51 #define CONFIG_83XX_CLKIN               66000000
  52 #define CONFIG_SYS_CLK_FREQ             66000000
  53 #define CONFIG_83XX_PCICLK              66000000
  54
  55 /*
  56  * IMMR new address
  57  */
  58 #define CONFIG_SYS_IMMR         0xE0000000
  59
  60 /*
  61  * Bus Arbitration Configuration Register (ACR)
  62  */
  63 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* pipeline depth 4 transactions */
  64 #define CONFIG_SYS_ACR_RPTCNT   3       /* 4 consecutive transactions */
  65 #define CONFIG_SYS_ACR_APARK    0       /* park bus to master (below) */
  66 #define CONFIG_SYS_ACR_PARKM    3       /* parking master = QuiccEngine */
  67
  68 /*
  69  * DDR Setup
  70  */
  71 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
  72 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  73 #define CONFIG_SYS_SDRAM_BASE2  (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
  74
  75 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  76 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN | \
  77                                         DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  78
  79 #define CFG_83XX_DDR_USES_CS0
  80
  81 /*
  82  * Manually set up DDR parameters
  83  */
  84 #define CONFIG_DDR_II
  85 #define CONFIG_SYS_DDR_SIZE             2048 /* MB */
  86
  87 /*
  88  * The reserved memory
  89  */
  90 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  91 #define CONFIG_SYS_FLASH_BASE           0xF0000000
  92
  93 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  94 #define CONFIG_SYS_RAMBOOT
  95 #endif
  96
  97 /* Reserve 768 kB for Mon */
  98 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
  99
 100 /*
 101  * Initial RAM Base Address Setup
 102  */
 103 #define CONFIG_SYS_INIT_RAM_LOCK
 104 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 105 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* End of used area in RAM */
 106 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 107                                                 GENERATED_GBL_DATA_SIZE)
 108
 109 /*
 110  * Init Local Bus Memory Controller:
 111  *
 112  * Bank Bus     Machine PortSz  Size  Device
 113  * ---- ---     ------- ------  -----  ------
 114  *  0   Local   GPCM    16 bit  256MB FLASH
 115  *  1   Local   GPCM     8 bit  128MB GPIO/PIGGY
 116  *
 117  */
 118 /*
 119  * FLASH on the Local Bus
 120  */
 121 #define CONFIG_SYS_FLASH_SIZE           256 /* max FLASH size is 256M */
 122
 123 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 124 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_256MB)
 125
 126 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE | \
 127                                 BR_PS_16 | /* 16 bit port size */ \
 128                                 BR_MS_GPCM | /* MSEL = GPCM */ \
 129                                 BR_V)
 130
 131 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
 132                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 133                                 OR_GPCM_SCY_5 | \
 134                                 OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 135
 136 #define CONFIG_SYS_MAX_FLASH_BANKS      1   /* max num of flash banks   */
 137 #define CONFIG_SYS_MAX_FLASH_SECT       512 /* max num of sects on one chip */
 138 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
 139
 140 /*
 141  * PRIO1/PIGGY on the local bus CS1
 142  */
 143 /* Window base at flash base */
 144 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_KMBEC_FPGA_BASE
 145 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_128MB)
 146
 147 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_KMBEC_FPGA_BASE | \
 148                                 BR_PS_8 | /* 8 bit port size */ \
 149                                 BR_MS_GPCM | /* MSEL = GPCM */ \
 150                                 BR_V)
 151 #define CONFIG_SYS_OR1_PRELIM   (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \
 152                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 153                                 OR_GPCM_SCY_2 | \
 154                                 OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 155
 156 /*
 157  * Serial Port
 158  */
 159 #define CONFIG_SYS_NS16550_SERIAL
 160 #define CONFIG_SYS_NS16550_REG_SIZE     1
 161 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 162
 163 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 164 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 165
 166 /*
 167  * QE UEC ethernet configuration
 168  */
 169 #define CONFIG_UEC_ETH
 170 #define CONFIG_ETHPRIME         "UEC0"
 171
 172 #ifdef CONFIG_UEC_ETH1
 173 #define CONFIG_SYS_UEC1_UCC_NUM 3       /* UCC4 */
 174 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK_NONE /* not used in RMII Mode */
 175 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK17
 176 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 177 #define CONFIG_SYS_UEC1_PHY_ADDR        0
 178 #define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_RMII
 179 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 180 #endif
 181
 182 /*
 183  * Environment
 184  */
 185
 186 #ifndef CONFIG_SYS_RAMBOOT
 187 #ifndef CONFIG_ENV_ADDR
 188 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 189                                         CONFIG_SYS_MONITOR_LEN)
 190 #endif
 191 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 192 #ifndef CONFIG_ENV_OFFSET
 193 #define CONFIG_ENV_OFFSET       (CONFIG_SYS_MONITOR_LEN)
 194 #endif
 195
 196 /* Address and size of Redundant Environment Sector     */
 197 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + \
 198                                                 CONFIG_ENV_SECT_SIZE)
 199 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 200
 201 #else /* CFG_SYS_RAMBOOT */
 202 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 203 #define CONFIG_ENV_SIZE         0x2000
 204 #endif /* CFG_SYS_RAMBOOT */
 205
 206 /* I2C */
 207 #define CONFIG_SYS_I2C
 208 #define CONFIG_SYS_NUM_I2C_BUSES        4
 209 #define CONFIG_SYS_I2C_MAX_HOPS         1
 210 #define CONFIG_SYS_I2C_FSL
 211 #define CONFIG_SYS_FSL_I2C_SPEED        200000
 212 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 213 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 214 #define CONFIG_SYS_I2C_OFFSET           0x3000
 215 #define CONFIG_SYS_FSL_I2C2_SPEED       200000
 216 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 217 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 218 #define CONFIG_SYS_I2C_BUSES    {{0, {I2C_NULL_HOP} }, \
 219                 {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
 220                 {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
 221                 {1, {I2C_NULL_HOP} } }
 222
 223 #define CONFIG_KM_IVM_BUS               2       /* I2C2 (Mux-Port 1)*/
 224
 225 #if defined(CONFIG_CMD_NAND)
 226 #define CONFIG_NAND_KMETER1
 227 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 228 #define CONFIG_SYS_NAND_BASE            CONFIG_SYS_KMBEC_FPGA_BASE
 229 #endif
 230
 231 /*
 232  * For booting Linux, the board info and command line data
 233  * have to be in the first 8 MB of memory, since this is
 234  * the maximum mapped by the Linux kernel during initialization.
 235  */
 236 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)
 237
 238 /*
 239  * Core HID Setup
 240  */
 241 #define CONFIG_SYS_HID0_INIT            0x000000000
 242 #define CONFIG_SYS_HID0_FINAL           (HID0_ENABLE_MACHINE_CHECK | \
 243                                          HID0_ENABLE_INSTRUCTION_CACHE)
 244 #define CONFIG_SYS_HID2                 HID2_HBE
 245
 246 /*
 247  * MMU Setup
 248  */
 249
 250 /* DDR: cache cacheable */
 251 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
 252                                 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 253 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
 254                                         BATU_VS | BATU_VP)
 255 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 256 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 257
 258 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
 259 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR | BATL_PP_RW | \
 260                                 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 261 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \
 262                                         | BATU_VP)
 263 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 264 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 265
 266 /* PRIO1, PIGGY:  icache cacheable, but dcache-inhibit and guarded */
 267 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
 268                                 BATL_MEMCOHERENCE)
 269 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \
 270                                 BATU_VS | BATU_VP)
 271 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
 272                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 273 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 274
 275 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 276 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
 277                                         BATL_MEMCOHERENCE)
 278 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \
 279                                         BATU_VS | BATU_VP)
 280 #define CONFIG_SYS_DBAT3L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
 281                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 282 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 283
 284 /* Stack in dcache: cacheable, no memory coherence */
 285 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 286 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
 287                                         BATU_VS | BATU_VP)
 288 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 289 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 290
 291 /*
 292  * Internal Definitions
 293  */
 294 #define BOOTFLASH_START 0xF0000000
 295
 296 #define CONFIG_KM_CONSOLE_TTY   "ttyS0"
 297
 298 /*
 299  * Environment Configuration
 300  */
 301 #define CONFIG_ENV_OVERWRITE
 302 #ifndef CONFIG_KM_DEF_ENV               /* if not set by keymile-common.h */
 303 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
 304 #endif
 305
 306 #ifndef CONFIG_KM_DEF_ARCH
 307 #define CONFIG_KM_DEF_ARCH      "arch=ppc_82xx\0"
 308 #endif
 309
 310 #define CONFIG_EXTRA_ENV_SETTINGS \
 311         CONFIG_KM_DEF_ENV                                               \
 312         CONFIG_KM_DEF_ARCH                                              \
 313         "newenv="                                                       \
 314                 "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && "  \
 315                 "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0"         \
 316         "unlock=yes\0"                                                  \
 317         ""
 318
 319 #if defined(CONFIG_UEC_ETH)
 320 #define CONFIG_HAS_ETH0
 321 #endif
 322
 323 /* QE microcode/firmware address */
 324 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 325 /* between the u-boot partition and env */
 326 #ifndef CONFIG_SYS_QE_FW_ADDR
 327 #define CONFIG_SYS_QE_FW_ADDR   0xF00C0000
 328 #endif
 329
 330 /*
 331  * System IO Config
 332  */
 333 /* 0x14000180 SICR_1 */
 334 #define CONFIG_SYS_SICRL (0                     \
 335                 | SICR_1_UART1_UART1RTS         \
 336                 | SICR_1_I2C_CKSTOP             \
 337                 | SICR_1_IRQ_A_IRQ              \
 338                 | SICR_1_IRQ_B_IRQ              \
 339                 | SICR_1_GPIO_A_GPIO            \
 340                 | SICR_1_GPIO_B_GPIO            \
 341                 | SICR_1_GPIO_C_GPIO            \
 342                 | SICR_1_GPIO_D_GPIO            \
 343                 | SICR_1_GPIO_E_GPIO            \
 344                 | SICR_1_GPIO_F_GPIO            \
 345                 | SICR_1_USB_A_UART2S           \
 346                 | SICR_1_USB_B_UART2RTS         \
 347                 | SICR_1_FEC1_FEC1              \
 348                 | SICR_1_FEC2_FEC2              \
 349                 )
 350
 351 /* 0x00080400 SICR_2 */
 352 #define CONFIG_SYS_SICRH (0                     \
 353                 | SICR_2_FEC3_FEC3              \
 354                 | SICR_2_HDLC1_A_HDLC1          \
 355                 | SICR_2_ELBC_A_LA              \
 356                 | SICR_2_ELBC_B_LCLK            \
 357                 | SICR_2_HDLC2_A_HDLC2          \
 358                 | SICR_2_USB_D_GPIO             \
 359                 | SICR_2_PCI_PCI                \
 360                 | SICR_2_HDLC1_B_HDLC1          \
 361                 | SICR_2_HDLC1_C_HDLC1          \
 362                 | SICR_2_HDLC2_B_GPIO           \
 363                 | SICR_2_HDLC2_C_HDLC2          \
 364                 | SICR_2_QUIESCE_B              \
 365                 )
 366
 367 /* GPR_1 */
 368 #define CONFIG_SYS_GPR1  0x50008060
 369
 370 #define CONFIG_SYS_GP1DIR 0x00000000
 371 #define CONFIG_SYS_GP1ODR 0x00000000
 372 #define CONFIG_SYS_GP2DIR 0xFF000000
 373 #define CONFIG_SYS_GP2ODR 0x00000000
 374
 375 #define CONFIG_SYS_DDRCDR (\
 376         DDRCDR_EN | \
 377         DDRCDR_PZ_MAXZ | \
 378         DDRCDR_NZ_MAXZ | \
 379         DDRCDR_M_ODR)
 380
 381 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000007f
 382 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
 383                                          SDRAM_CFG_32_BE | \
 384                                          SDRAM_CFG_SREN | \
 385                                          SDRAM_CFG_HSE)
 386
 387 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
 388 #define CONFIG_SYS_DDR_CLK_CNTL         (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 389 #define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
 390                                  (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
 391
 392 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN | CSCONFIG_AP | \
 393                                          CSCONFIG_ODT_RD_NEVER | \
 394                                          CSCONFIG_ODT_WR_ONLY_CURRENT | \
 395                                          CSCONFIG_ROW_BIT_13 | \
 396                                          CSCONFIG_COL_BIT_10)
 397
 398 #define CONFIG_SYS_DDR_MODE     0x47860242
 399 #define CONFIG_SYS_DDR_MODE2    0x8080c000
 400
 401 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
 402                                  (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
 403                                  (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
 404                                  (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
 405                                  (0 << TIMING_CFG0_WWT_SHIFT) | \
 406                                  (0 << TIMING_CFG0_RRT_SHIFT) | \
 407                                  (0 << TIMING_CFG0_WRT_SHIFT) | \
 408                                  (0 << TIMING_CFG0_RWT_SHIFT))
 409
 410 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
 411                                  (2 << TIMING_CFG1_WRTORD_SHIFT) | \
 412                                  (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
 413                                  (3 << TIMING_CFG1_WRREC_SHIFT) | \
 414                                  (7 << TIMING_CFG1_REFREC_SHIFT) | \
 415                                  (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
 416                                  (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
 417                                  (3 << TIMING_CFG1_PRETOACT_SHIFT))
 418
 419 #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
 420                                  (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
 421                                  (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
 422                                  (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
 423                                  (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
 424                                  (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
 425                                  (5 << TIMING_CFG2_CPO_SHIFT))
 426
 427 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 428
 429 #define CONFIG_SYS_KMBEC_FPGA_BASE      0xE8000000
 430 #define CONFIG_SYS_KMBEC_FPGA_SIZE      128
 431
 432 /* EEprom support */
 433 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 434
 435 /*
 436  * Local Bus Configuration & Clock Setup
 437  */
 438 #define CONFIG_SYS_LCRR_DBYP    0x80000000
 439 #define CONFIG_SYS_LCRR_EADC    0x00010000
 440 #define CONFIG_SYS_LCRR_CLKDIV  0x00000002
 441
 442 #define CONFIG_SYS_LBC_LBCR     0x00000000
 443
 444 /*
 445  * MMU Setup
 446  */
 447 #define CONFIG_SYS_IBAT7L       (0)
 448 #define CONFIG_SYS_IBAT7U       (0)
 449 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 450 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 451
 452 /* must be after the include because KMBEC_FPGA is otherwise undefined */
 453 #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
 454
 455 #define CONFIG_SYS_APP1_BASE            0xA0000000
 456 #define CONFIG_SYS_APP1_SIZE            256 /* Megabytes */
 457 #define CONFIG_SYS_APP2_BASE            0xB0000000
 458 #define CONFIG_SYS_APP2_SIZE            256 /* Megabytes */
 459
 460 /* EEprom support */
 461 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 462
 463 /*
 464  * Init Local Bus Memory Controller:
 465  *
 466  * Bank Bus     Machine PortSz  Size  Device
 467  * ---- ---     ------- ------  -----  ------
 468  *  2   Local   UPMA    16 bit  256MB APP1
 469  *  3   Local   GPCM    16 bit  256MB APP2
 470  *
 471  */
 472
 473 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \
 474                                  BR_PS_16 | \
 475                                  BR_MS_GPCM | \
 476                                  BR_V)
 477
 478 #define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
 479                                  OR_GPCM_SCY_5 | \
 480                                  OR_GPCM_TRLX_CLEAR | \
 481                                  OR_GPCM_EHTR_CLEAR)
 482
 483 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_APP2_BASE
 484 #define CONFIG_SYS_LBLAWAR3_PRELIM      (LBLAWAR_EN | LBLAWAR_256MB)
 485
 486 /*
 487  * MMU Setup
 488  */
 489 #define CONFIG_SYS_IBAT5L (0)
 490 #define CONFIG_SYS_IBAT5U (0)
 491 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
 492 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
 493 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \
 494                                  BATL_MEMCOHERENCE)
 495 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_APP2_BASE | BATU_BL_256M | \
 496                                  BATU_VS | BATU_VP)
 497 #define CONFIG_SYS_DBAT6L       (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \
 498                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 499 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 500
 501 /* ethernet port connected to piggy (UEC2) */
 502 #define CONFIG_HAS_ETH1
 503 #define CONFIG_UEC_ETH2
 504 #define CONFIG_SYS_UEC2_UCC_NUM         2       /* UCC3 */
 505 #define CONFIG_SYS_UEC2_RX_CLK          QE_CLK_NONE /* not used in RMII Mode */
 506 #define CONFIG_SYS_UEC2_TX_CLK          QE_CLK12
 507 #define CONFIG_SYS_UEC2_ETH_TYPE        FAST_ETH
 508 #define CONFIG_SYS_UEC2_PHY_ADDR        0
 509 #define CONFIG_SYS_UEC2_INTERFACE_TYPE  PHY_INTERFACE_MODE_RMII
 510 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
 511
 512 #endif /* __CONFIG_H */