include/configs/kmtegr1.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   4  *                    Dave Liu <daveliu@freescale.com>
   5  *
   6  * Copyright (C) 2007 Logic Product Development, Inc.
   7  *                    Peter Barada <peterb@logicpd.com>
   8  *
   9  * Copyright (C) 2007 MontaVista Software, Inc.
  10  *                    Anton Vorontsov <avorontsov@ru.mvista.com>
  11  *
  12  * (C) Copyright 2010
  13  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  14  */
  15
  16 #ifndef __CONFIG_H
  17 #define __CONFIG_H
  18
  19 /*
  20  * High Level Configuration Options
  21  */
  22
  23 #define CONFIG_HOSTNAME   "kmtegr1"
  24 #define CONFIG_KM_BOARD_NAME   "kmtegr1"
  25 #define CONFIG_KM_UBI_PARTITION_NAME_BOOT       "ubi0"
  26 #define CONFIG_KM_UBI_PARTITION_NAME_APP        "ubi1"
  27
  28 #define CONFIG_ENV_ADDR         0xF0100000
  29 #define CONFIG_ENV_OFFSET       0x100000
  30
  31 #define CONFIG_NAND_ECC_BCH
  32 #define CONFIG_NAND_KMETER1
  33 #define CONFIG_SYS_MAX_NAND_DEVICE              1
  34 #define NAND_MAX_CHIPS                          1
  35
  36 /*
  37  * High Level Configuration Options
  38  */
  39 #define CONFIG_E300             1       /* E300 family */
  40 #define CONFIG_QE               1       /* Has QE */
  41
  42 #define CONFIG_KM_DEF_ARCH      "arch=ppc_82xx\0"
  43
  44 /* include common defines/options for all Keymile boards */
  45 #include "km/keymile-common.h"
  46 #include "km/km-powerpc.h"
  47
  48 /*
  49  * System Clock Setup
  50  */
  51 #define CONFIG_83XX_CLKIN               66000000
  52 #define CONFIG_SYS_CLK_FREQ             66000000
  53 #define CONFIG_83XX_PCICLK              66000000
  54
  55 /*
  56  * DDR Setup
  57  */
  58 #define CONFIG_SYS_SDRAM_BASE           0x00000000 /* DDR is system memory */
  59 #define CONFIG_SYS_SDRAM_BASE2  (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
  60
  61 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN | \
  62                                         DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  63
  64 #define CFG_83XX_DDR_USES_CS0
  65
  66 /*
  67  * Manually set up DDR parameters
  68  */
  69 #define CONFIG_DDR_II
  70 #define CONFIG_SYS_DDR_SIZE             2048 /* MB */
  71
  72 /*
  73  * The reserved memory
  74  */
  75 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  76 #define CONFIG_SYS_FLASH_BASE           0xF0000000
  77
  78 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  79 #define CONFIG_SYS_RAMBOOT
  80 #endif
  81
  82 /* Reserve 768 kB for Mon */
  83 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
  84
  85 /*
  86  * Initial RAM Base Address Setup
  87  */
  88 #define CONFIG_SYS_INIT_RAM_LOCK
  89 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
  90 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* End of used area in RAM */
  91 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
  92                                                 GENERATED_GBL_DATA_SIZE)
  93
  94 /*
  95  * Init Local Bus Memory Controller:
  96  *
  97  * Bank Bus     Machine PortSz  Size  Device
  98  * ---- ---     ------- ------  -----  ------
  99  *  0   Local   GPCM    16 bit  256MB FLASH
 100  *  1   Local   GPCM     8 bit  128MB GPIO/PIGGY
 101  *
 102  */
 103 /*
 104  * FLASH on the Local Bus
 105  */
 106 #define CONFIG_SYS_FLASH_SIZE           256 /* max FLASH size is 256M */
 107
 108
 109 #define CONFIG_SYS_MAX_FLASH_BANKS      1   /* max num of flash banks   */
 110 #define CONFIG_SYS_MAX_FLASH_SECT       512 /* max num of sects on one chip */
 111 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
 112
 113 /*
 114  * PRIO1/PIGGY on the local bus CS1
 115  */
 116
 117
 118 /*
 119  * Serial Port
 120  */
 121 #define CONFIG_SYS_NS16550_SERIAL
 122 #define CONFIG_SYS_NS16550_REG_SIZE     1
 123 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 124
 125 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 126 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 127
 128 /*
 129  * QE UEC ethernet configuration
 130  */
 131 #define CONFIG_UEC_ETH
 132 #define CONFIG_ETHPRIME         "UEC0"
 133
 134 #ifdef CONFIG_UEC_ETH1
 135 #define CONFIG_SYS_UEC1_UCC_NUM 3       /* UCC4 */
 136 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK_NONE /* not used in RMII Mode */
 137 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK17
 138 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 139 #define CONFIG_SYS_UEC1_PHY_ADDR        0
 140 #define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_RMII
 141 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 142 #endif
 143
 144 /*
 145  * Environment
 146  */
 147
 148 #ifndef CONFIG_SYS_RAMBOOT
 149 #ifndef CONFIG_ENV_ADDR
 150 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 151                                         CONFIG_SYS_MONITOR_LEN)
 152 #endif
 153 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 154 #ifndef CONFIG_ENV_OFFSET
 155 #define CONFIG_ENV_OFFSET       (CONFIG_SYS_MONITOR_LEN)
 156 #endif
 157
 158 /* Address and size of Redundant Environment Sector     */
 159 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + \
 160                                                 CONFIG_ENV_SECT_SIZE)
 161 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 162
 163 #else /* CFG_SYS_RAMBOOT */
 164 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 165 #define CONFIG_ENV_SIZE         0x2000
 166 #endif /* CFG_SYS_RAMBOOT */
 167
 168 /* I2C */
 169 #define CONFIG_SYS_I2C
 170 #define CONFIG_SYS_NUM_I2C_BUSES        4
 171 #define CONFIG_SYS_I2C_MAX_HOPS         1
 172 #define CONFIG_SYS_I2C_FSL
 173 #define CONFIG_SYS_FSL_I2C_SPEED        200000
 174 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 175 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 176 #define CONFIG_SYS_I2C_OFFSET           0x3000
 177 #define CONFIG_SYS_FSL_I2C2_SPEED       200000
 178 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 179 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 180 #define CONFIG_SYS_I2C_BUSES    {{0, {I2C_NULL_HOP} }, \
 181                 {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
 182                 {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
 183                 {1, {I2C_NULL_HOP} } }
 184
 185 #define CONFIG_KM_IVM_BUS               2       /* I2C2 (Mux-Port 1)*/
 186
 187 #if defined(CONFIG_CMD_NAND)
 188 #define CONFIG_NAND_KMETER1
 189 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 190 #define CONFIG_SYS_NAND_BASE            CONFIG_SYS_KMBEC_FPGA_BASE
 191 #endif
 192
 193 /*
 194  * For booting Linux, the board info and command line data
 195  * have to be in the first 8 MB of memory, since this is
 196  * the maximum mapped by the Linux kernel during initialization.
 197  */
 198 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)
 199
 200 /*
 201  * Internal Definitions
 202  */
 203 #define BOOTFLASH_START 0xF0000000
 204
 205 #define CONFIG_KM_CONSOLE_TTY   "ttyS0"
 206
 207 /*
 208  * Environment Configuration
 209  */
 210 #define CONFIG_ENV_OVERWRITE
 211 #ifndef CONFIG_KM_DEF_ENV               /* if not set by keymile-common.h */
 212 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
 213 #endif
 214
 215 #ifndef CONFIG_KM_DEF_ARCH
 216 #define CONFIG_KM_DEF_ARCH      "arch=ppc_82xx\0"
 217 #endif
 218
 219 #define CONFIG_EXTRA_ENV_SETTINGS \
 220         CONFIG_KM_DEF_ENV                                               \
 221         CONFIG_KM_DEF_ARCH                                              \
 222         "newenv="                                                       \
 223                 "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && "  \
 224                 "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0"         \
 225         "unlock=yes\0"                                                  \
 226         ""
 227
 228 #if defined(CONFIG_UEC_ETH)
 229 #define CONFIG_HAS_ETH0
 230 #endif
 231
 232 /* QE microcode/firmware address */
 233 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 234 /* between the u-boot partition and env */
 235 #ifndef CONFIG_SYS_QE_FW_ADDR
 236 #define CONFIG_SYS_QE_FW_ADDR   0xF00C0000
 237 #endif
 238
 239 /*
 240  * System IO Config
 241  */
 242 /* 0x14000180 SICR_1 */
 243 #define CONFIG_SYS_SICRL (0                     \
 244                 | SICR_1_UART1_UART1RTS         \
 245                 | SICR_1_I2C_CKSTOP             \
 246                 | SICR_1_IRQ_A_IRQ              \
 247                 | SICR_1_IRQ_B_IRQ              \
 248                 | SICR_1_GPIO_A_GPIO            \
 249                 | SICR_1_GPIO_B_GPIO            \
 250                 | SICR_1_GPIO_C_GPIO            \
 251                 | SICR_1_GPIO_D_GPIO            \
 252                 | SICR_1_GPIO_E_GPIO            \
 253                 | SICR_1_GPIO_F_GPIO            \
 254                 | SICR_1_USB_A_UART2S           \
 255                 | SICR_1_USB_B_UART2RTS         \
 256                 | SICR_1_FEC1_FEC1              \
 257                 | SICR_1_FEC2_FEC2              \
 258                 )
 259
 260 /* 0x00080400 SICR_2 */
 261 #define CONFIG_SYS_SICRH (0                     \
 262                 | SICR_2_FEC3_FEC3              \
 263                 | SICR_2_HDLC1_A_HDLC1          \
 264                 | SICR_2_ELBC_A_LA              \
 265                 | SICR_2_ELBC_B_LCLK            \
 266                 | SICR_2_HDLC2_A_HDLC2          \
 267                 | SICR_2_USB_D_GPIO             \
 268                 | SICR_2_PCI_PCI                \
 269                 | SICR_2_HDLC1_B_HDLC1          \
 270                 | SICR_2_HDLC1_C_HDLC1          \
 271                 | SICR_2_HDLC2_B_GPIO           \
 272                 | SICR_2_HDLC2_C_HDLC2          \
 273                 | SICR_2_QUIESCE_B              \
 274                 )
 275
 276 /* GPR_1 */
 277 #define CONFIG_SYS_GPR1  0x50008060
 278
 279 #define CONFIG_SYS_GP1DIR 0x00000000
 280 #define CONFIG_SYS_GP1ODR 0x00000000
 281 #define CONFIG_SYS_GP2DIR 0xFF000000
 282 #define CONFIG_SYS_GP2ODR 0x00000000
 283
 284 #define CONFIG_SYS_DDRCDR (\
 285         DDRCDR_EN | \
 286         DDRCDR_PZ_MAXZ | \
 287         DDRCDR_NZ_MAXZ | \
 288         DDRCDR_M_ODR)
 289
 290 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000007f
 291 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
 292                                          SDRAM_CFG_32_BE | \
 293                                          SDRAM_CFG_SREN | \
 294                                          SDRAM_CFG_HSE)
 295
 296 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
 297 #define CONFIG_SYS_DDR_CLK_CNTL         (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 298 #define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
 299                                  (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
 300
 301 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN | CSCONFIG_AP | \
 302                                          CSCONFIG_ODT_RD_NEVER | \
 303                                          CSCONFIG_ODT_WR_ONLY_CURRENT | \
 304                                          CSCONFIG_ROW_BIT_13 | \
 305                                          CSCONFIG_COL_BIT_10)
 306
 307 #define CONFIG_SYS_DDR_MODE     0x47860242
 308 #define CONFIG_SYS_DDR_MODE2    0x8080c000
 309
 310 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
 311                                  (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
 312                                  (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
 313                                  (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
 314                                  (0 << TIMING_CFG0_WWT_SHIFT) | \
 315                                  (0 << TIMING_CFG0_RRT_SHIFT) | \
 316                                  (0 << TIMING_CFG0_WRT_SHIFT) | \
 317                                  (0 << TIMING_CFG0_RWT_SHIFT))
 318
 319 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
 320                                  (2 << TIMING_CFG1_WRTORD_SHIFT) | \
 321                                  (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
 322                                  (3 << TIMING_CFG1_WRREC_SHIFT) | \
 323                                  (7 << TIMING_CFG1_REFREC_SHIFT) | \
 324                                  (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
 325                                  (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
 326                                  (3 << TIMING_CFG1_PRETOACT_SHIFT))
 327
 328 #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
 329                                  (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
 330                                  (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
 331                                  (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
 332                                  (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
 333                                  (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
 334                                  (5 << TIMING_CFG2_CPO_SHIFT))
 335
 336 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 337
 338 #define CONFIG_SYS_KMBEC_FPGA_BASE      0xE8000000
 339 #define CONFIG_SYS_KMBEC_FPGA_SIZE      128
 340
 341 /* EEprom support */
 342 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 343
 344 /* must be after the include because KMBEC_FPGA is otherwise undefined */
 345 #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
 346
 347 #define CONFIG_SYS_APP1_BASE            0xA0000000
 348 #define CONFIG_SYS_APP1_SIZE            256 /* Megabytes */
 349 #define CONFIG_SYS_APP2_BASE            0xB0000000
 350 #define CONFIG_SYS_APP2_SIZE            256 /* Megabytes */
 351
 352 /* EEprom support */
 353 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 354
 355 /*
 356  * Init Local Bus Memory Controller:
 357  *
 358  * Bank Bus     Machine PortSz  Size  Device
 359  * ---- ---     ------- ------  -----  ------
 360  *  2   Local   UPMA    16 bit  256MB APP1
 361  *  3   Local   GPCM    16 bit  256MB APP2
 362  *
 363  */
 364
 365
 366 /* ethernet port connected to piggy (UEC2) */
 367 #define CONFIG_HAS_ETH1
 368 #define CONFIG_UEC_ETH2
 369 #define CONFIG_SYS_UEC2_UCC_NUM         2       /* UCC3 */
 370 #define CONFIG_SYS_UEC2_RX_CLK          QE_CLK_NONE /* not used in RMII Mode */
 371 #define CONFIG_SYS_UEC2_TX_CLK          QE_CLK12
 372 #define CONFIG_SYS_UEC2_ETH_TYPE        FAST_ETH
 373 #define CONFIG_SYS_UEC2_PHY_ADDR        0
 374 #define CONFIG_SYS_UEC2_INTERFACE_TYPE  PHY_INTERFACE_MODE_RMII
 375 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
 376
 377 #endif /* __CONFIG_H */