include/configs/kmtegr1.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   4  *                    Dave Liu <daveliu@freescale.com>
   5  *
   6  * Copyright (C) 2007 Logic Product Development, Inc.
   7  *                    Peter Barada <peterb@logicpd.com>
   8  *
   9  * Copyright (C) 2007 MontaVista Software, Inc.
  10  *                    Anton Vorontsov <avorontsov@ru.mvista.com>
  11  *
  12  * (C) Copyright 2010
  13  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  14  */
  15
  16 #ifndef __CONFIG_H
  17 #define __CONFIG_H
  18
  19 /*
  20  * High Level Configuration Options
  21  */
  22
  23 /* This needs to be set prior to including km83xx-common.h */
  24
  25 #define CONFIG_HOSTNAME   "kmtegr1"
  26 #define CONFIG_KM_BOARD_NAME   "kmtegr1"
  27 #define CONFIG_KM_UBI_PARTITION_NAME_BOOT       "ubi0"
  28 #define CONFIG_KM_UBI_PARTITION_NAME_APP        "ubi1"
  29
  30 #define CONFIG_ENV_ADDR         0xF0100000
  31 #define CONFIG_ENV_OFFSET       0x100000
  32
  33 #define CONFIG_NAND_ECC_BCH
  34 #define CONFIG_NAND_KMETER1
  35 #define CONFIG_SYS_MAX_NAND_DEVICE              1
  36 #define NAND_MAX_CHIPS                          1
  37
  38 /*
  39  * High Level Configuration Options
  40  */
  41 #define CONFIG_E300             1       /* E300 family */
  42 #define CONFIG_QE               1       /* Has QE */
  43
  44 #define CONFIG_KM_DEF_ARCH      "arch=ppc_82xx\0"
  45
  46 /* include common defines/options for all 83xx Keymile boards */
  47 #include "km83xx-common.h"
  48
  49 /* QE microcode/firmware address */
  50 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
  51 /* between the u-boot partition and env */
  52 #ifndef CONFIG_SYS_QE_FW_ADDR
  53 #define CONFIG_SYS_QE_FW_ADDR   0xF00C0000
  54 #endif
  55
  56 /*
  57  * System IO Config
  58  */
  59 /* 0x14000180 SICR_1 */
  60 #define CONFIG_SYS_SICRL (0                     \
  61                 | SICR_1_UART1_UART1RTS         \
  62                 | SICR_1_I2C_CKSTOP             \
  63                 | SICR_1_IRQ_A_IRQ              \
  64                 | SICR_1_IRQ_B_IRQ              \
  65                 | SICR_1_GPIO_A_GPIO            \
  66                 | SICR_1_GPIO_B_GPIO            \
  67                 | SICR_1_GPIO_C_GPIO            \
  68                 | SICR_1_GPIO_D_GPIO            \
  69                 | SICR_1_GPIO_E_GPIO            \
  70                 | SICR_1_GPIO_F_GPIO            \
  71                 | SICR_1_USB_A_UART2S           \
  72                 | SICR_1_USB_B_UART2RTS         \
  73                 | SICR_1_FEC1_FEC1              \
  74                 | SICR_1_FEC2_FEC2              \
  75                 )
  76
  77 /* 0x00080400 SICR_2 */
  78 #define CONFIG_SYS_SICRH (0                     \
  79                 | SICR_2_FEC3_FEC3              \
  80                 | SICR_2_HDLC1_A_HDLC1          \
  81                 | SICR_2_ELBC_A_LA              \
  82                 | SICR_2_ELBC_B_LCLK            \
  83                 | SICR_2_HDLC2_A_HDLC2          \
  84                 | SICR_2_USB_D_GPIO             \
  85                 | SICR_2_PCI_PCI                \
  86                 | SICR_2_HDLC1_B_HDLC1          \
  87                 | SICR_2_HDLC1_C_HDLC1          \
  88                 | SICR_2_HDLC2_B_GPIO           \
  89                 | SICR_2_HDLC2_C_HDLC2          \
  90                 | SICR_2_QUIESCE_B              \
  91                 )
  92
  93 /* GPR_1 */
  94 #define CONFIG_SYS_GPR1  0x50008060
  95
  96 #define CONFIG_SYS_GP1DIR 0x00000000
  97 #define CONFIG_SYS_GP1ODR 0x00000000
  98 #define CONFIG_SYS_GP2DIR 0xFF000000
  99 #define CONFIG_SYS_GP2ODR 0x00000000
 100
 101 /*
 102  * Hardware Reset Configuration Word
 103  */
 104 #define CONFIG_SYS_HRCW_LOW (\
 105         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
 106         HRCWL_DDR_TO_SCB_CLK_2X1 | \
 107         HRCWL_CSB_TO_CLKIN_2X1 | \
 108         HRCWL_CORE_TO_CSB_2X1 | \
 109         HRCWL_CE_PLL_VCO_DIV_2 | \
 110         HRCWL_CE_TO_PLL_1X3)
 111
 112 #define CONFIG_SYS_HRCW_HIGH (\
 113         HRCWH_PCI_AGENT | \
 114         HRCWH_PCI_ARBITER_DISABLE | \
 115         HRCWH_CORE_ENABLE | \
 116         HRCWH_FROM_0X00000100 | \
 117         HRCWH_BOOTSEQ_DISABLE | \
 118         HRCWH_SW_WATCHDOG_DISABLE | \
 119         HRCWH_ROM_LOC_LOCAL_16BIT | \
 120         HRCWH_BIG_ENDIAN | \
 121         HRCWH_LALE_NORMAL)
 122
 123 #define CONFIG_SYS_DDRCDR (\
 124         DDRCDR_EN | \
 125         DDRCDR_PZ_MAXZ | \
 126         DDRCDR_NZ_MAXZ | \
 127         DDRCDR_M_ODR)
 128
 129 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000007f
 130 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
 131                                          SDRAM_CFG_32_BE | \
 132                                          SDRAM_CFG_SREN | \
 133                                          SDRAM_CFG_HSE)
 134
 135 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
 136 #define CONFIG_SYS_DDR_CLK_CNTL         (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 137 #define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
 138                                  (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
 139
 140 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN | CSCONFIG_AP | \
 141                                          CSCONFIG_ODT_RD_NEVER | \
 142                                          CSCONFIG_ODT_WR_ONLY_CURRENT | \
 143                                          CSCONFIG_ROW_BIT_13 | \
 144                                          CSCONFIG_COL_BIT_10)
 145
 146 #define CONFIG_SYS_DDR_MODE     0x47860242
 147 #define CONFIG_SYS_DDR_MODE2    0x8080c000
 148
 149 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
 150                                  (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
 151                                  (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
 152                                  (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
 153                                  (0 << TIMING_CFG0_WWT_SHIFT) | \
 154                                  (0 << TIMING_CFG0_RRT_SHIFT) | \
 155                                  (0 << TIMING_CFG0_WRT_SHIFT) | \
 156                                  (0 << TIMING_CFG0_RWT_SHIFT))
 157
 158 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
 159                                  (2 << TIMING_CFG1_WRTORD_SHIFT) | \
 160                                  (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
 161                                  (3 << TIMING_CFG1_WRREC_SHIFT) | \
 162                                  (7 << TIMING_CFG1_REFREC_SHIFT) | \
 163                                  (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
 164                                  (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
 165                                  (3 << TIMING_CFG1_PRETOACT_SHIFT))
 166
 167 #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
 168                                  (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
 169                                  (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
 170                                  (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
 171                                  (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
 172                                  (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
 173                                  (5 << TIMING_CFG2_CPO_SHIFT))
 174
 175 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 176
 177 #define CONFIG_SYS_KMBEC_FPGA_BASE      0xE8000000
 178 #define CONFIG_SYS_KMBEC_FPGA_SIZE      128
 179
 180 /* EEprom support */
 181 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 182
 183 /*
 184  * Local Bus Configuration & Clock Setup
 185  */
 186 #define CONFIG_SYS_LCRR_DBYP    0x80000000
 187 #define CONFIG_SYS_LCRR_EADC    0x00010000
 188 #define CONFIG_SYS_LCRR_CLKDIV  0x00000002
 189
 190 #define CONFIG_SYS_LBC_LBCR     0x00000000
 191
 192 /*
 193  * MMU Setup
 194  */
 195 #define CONFIG_SYS_IBAT7L       (0)
 196 #define CONFIG_SYS_IBAT7U       (0)
 197 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 198 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 199
 200 /* must be after the include because KMBEC_FPGA is otherwise undefined */
 201 #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
 202
 203 #define CONFIG_SYS_APP1_BASE            0xA0000000
 204 #define CONFIG_SYS_APP1_SIZE            256 /* Megabytes */
 205 #define CONFIG_SYS_APP2_BASE            0xB0000000
 206 #define CONFIG_SYS_APP2_SIZE            256 /* Megabytes */
 207
 208 /* EEprom support */
 209 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 210
 211 /*
 212  * Init Local Bus Memory Controller:
 213  *
 214  * Bank Bus     Machine PortSz  Size  Device
 215  * ---- ---     ------- ------  -----  ------
 216  *  2   Local   UPMA    16 bit  256MB APP1
 217  *  3   Local   GPCM    16 bit  256MB APP2
 218  *
 219  */
 220
 221 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \
 222                                  BR_PS_16 | \
 223                                  BR_MS_GPCM | \
 224                                  BR_V)
 225
 226 #define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
 227                                  OR_GPCM_SCY_5 | \
 228                                  OR_GPCM_TRLX_CLEAR | \
 229                                  OR_GPCM_EHTR_CLEAR)
 230
 231 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_APP2_BASE
 232 #define CONFIG_SYS_LBLAWAR3_PRELIM      (LBLAWAR_EN | LBLAWAR_256MB)
 233
 234 /*
 235  * MMU Setup
 236  */
 237 #define CONFIG_SYS_IBAT5L (0)
 238 #define CONFIG_SYS_IBAT5U (0)
 239 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
 240 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
 241 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \
 242                                  BATL_MEMCOHERENCE)
 243 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_APP2_BASE | BATU_BL_256M | \
 244                                  BATU_VS | BATU_VP)
 245 #define CONFIG_SYS_DBAT6L       (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \
 246                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 247 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 248
 249 /* ethernet port connected to piggy (UEC2) */
 250 #define CONFIG_HAS_ETH1
 251 #define CONFIG_UEC_ETH2
 252 #define CONFIG_SYS_UEC2_UCC_NUM         2       /* UCC3 */
 253 #define CONFIG_SYS_UEC2_RX_CLK          QE_CLK_NONE /* not used in RMII Mode */
 254 #define CONFIG_SYS_UEC2_TX_CLK          QE_CLK12
 255 #define CONFIG_SYS_UEC2_ETH_TYPE        FAST_ETH
 256 #define CONFIG_SYS_UEC2_PHY_ADDR        0
 257 #define CONFIG_SYS_UEC2_INTERFACE_TYPE  PHY_INTERFACE_MODE_RMII
 258 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
 259
 260 #endif /* __CONFIG_H */