include/configs/kmtegr1.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   4  *                    Dave Liu <daveliu@freescale.com>
   5  *
   6  * Copyright (C) 2007 Logic Product Development, Inc.
   7  *                    Peter Barada <peterb@logicpd.com>
   8  *
   9  * Copyright (C) 2007 MontaVista Software, Inc.
  10  *                    Anton Vorontsov <avorontsov@ru.mvista.com>
  11  *
  12  * (C) Copyright 2010
  13  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  14  */
  15
  16 #ifndef __CONFIG_H
  17 #define __CONFIG_H
  18
  19 /*
  20  * High Level Configuration Options
  21  */
  22
  23 /* This needs to be set prior to including km/km83xx-common.h */
  24
  25 #define CONFIG_HOSTNAME   "kmtegr1"
  26 #define CONFIG_KM_BOARD_NAME   "kmtegr1"
  27 #define CONFIG_KM_UBI_PARTITION_NAME_BOOT       "ubi0"
  28 #define CONFIG_KM_UBI_PARTITION_NAME_APP        "ubi1"
  29
  30 #define CONFIG_ENV_ADDR         0xF0100000
  31 #define CONFIG_ENV_OFFSET       0x100000
  32
  33 #define CONFIG_NAND_ECC_BCH
  34 #define CONFIG_NAND_KMETER1
  35 #define CONFIG_SYS_MAX_NAND_DEVICE              1
  36 #define NAND_MAX_CHIPS                          1
  37
  38 /* include common defines/options for all 8309 Keymile boards */
  39 #include "km/km8309-common.h"
  40 /* must be after the include because KMBEC_FPGA is otherwise undefined */
  41 #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
  42
  43 #define CONFIG_SYS_APP1_BASE            0xA0000000
  44 #define CONFIG_SYS_APP1_SIZE            256 /* Megabytes */
  45 #define CONFIG_SYS_APP2_BASE            0xB0000000
  46 #define CONFIG_SYS_APP2_SIZE            256 /* Megabytes */
  47
  48 /* EEprom support */
  49 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
  50
  51 /*
  52  * Init Local Bus Memory Controller:
  53  *
  54  * Bank Bus     Machine PortSz  Size  Device
  55  * ---- ---     ------- ------  -----  ------
  56  *  2   Local   UPMA    16 bit  256MB APP1
  57  *  3   Local   GPCM    16 bit  256MB APP2
  58  *
  59  */
  60
  61 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \
  62                                  BR_PS_16 | \
  63                                  BR_MS_GPCM | \
  64                                  BR_V)
  65
  66 #define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
  67                                  OR_GPCM_SCY_5 | \
  68                                  OR_GPCM_TRLX_CLEAR | \
  69                                  OR_GPCM_EHTR_CLEAR)
  70
  71 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_APP2_BASE
  72 #define CONFIG_SYS_LBLAWAR3_PRELIM      (LBLAWAR_EN | LBLAWAR_256MB)
  73
  74 /*
  75  * MMU Setup
  76  */
  77 #define CONFIG_SYS_IBAT5L (0)
  78 #define CONFIG_SYS_IBAT5U (0)
  79 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
  80 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
  81 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \
  82                                  BATL_MEMCOHERENCE)
  83 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_APP2_BASE | BATU_BL_256M | \
  84                                  BATU_VS | BATU_VP)
  85 #define CONFIG_SYS_DBAT6L       (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \
  86                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
  87 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
  88
  89 /* ethernet port connected to piggy (UEC2) */
  90 #define CONFIG_HAS_ETH1
  91 #define CONFIG_UEC_ETH2
  92 #define CONFIG_SYS_UEC2_UCC_NUM         2       /* UCC3 */
  93 #define CONFIG_SYS_UEC2_RX_CLK          QE_CLK_NONE /* not used in RMII Mode */
  94 #define CONFIG_SYS_UEC2_TX_CLK          QE_CLK12
  95 #define CONFIG_SYS_UEC2_ETH_TYPE        FAST_ETH
  96 #define CONFIG_SYS_UEC2_PHY_ADDR        0
  97 #define CONFIG_SYS_UEC2_INTERFACE_TYPE  PHY_INTERFACE_MODE_RMII
  98 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
  99
 100 #endif /* __CONFIG_H */