1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2006 Freescale Semiconductor, Inc.
4 * Dave Liu <daveliu@freescale.com>
6 * Copyright (C) 2007 Logic Product Development, Inc.
7 * Peter Barada <peterb@logicpd.com>
9 * Copyright (C) 2007 MontaVista Software, Inc.
10 * Anton Vorontsov <avorontsov@ru.mvista.com>
13 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
20 * High Level Configuration Options
23 #define CONFIG_HOSTNAME "kmtegr1"
24 #define CONFIG_KM_BOARD_NAME "kmtegr1"
25 #define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0"
26 #define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1"
28 #define CONFIG_ENV_ADDR 0xF0100000
29 #define CONFIG_ENV_OFFSET 0x100000
31 #define CONFIG_NAND_ECC_BCH
32 #define CONFIG_NAND_KMETER1
33 #define CONFIG_SYS_MAX_NAND_DEVICE 1
34 #define NAND_MAX_CHIPS 1
37 * High Level Configuration Options
39 #define CONFIG_E300 1 /* E300 family */
40 #define CONFIG_QE 1 /* Has QE */
42 #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
44 /* include common defines/options for all Keymile boards */
45 #include "km/keymile-common.h"
46 #include "km/km-powerpc.h"
51 #define CONFIG_83XX_CLKIN 66000000
52 #define CONFIG_SYS_CLK_FREQ 66000000
53 #define CONFIG_83XX_PCICLK 66000000
58 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
59 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
60 #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
62 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
63 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
64 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
66 #define CFG_83XX_DDR_USES_CS0
69 * Manually set up DDR parameters
72 #define CONFIG_SYS_DDR_SIZE 2048 /* MB */
77 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
78 #define CONFIG_SYS_FLASH_BASE 0xF0000000
80 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
81 #define CONFIG_SYS_RAMBOOT
84 /* Reserve 768 kB for Mon */
85 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
88 * Initial RAM Base Address Setup
90 #define CONFIG_SYS_INIT_RAM_LOCK
91 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
92 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */
93 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
94 GENERATED_GBL_DATA_SIZE)
97 * Init Local Bus Memory Controller:
99 * Bank Bus Machine PortSz Size Device
100 * ---- --- ------- ------ ----- ------
101 * 0 Local GPCM 16 bit 256MB FLASH
102 * 1 Local GPCM 8 bit 128MB GPIO/PIGGY
106 * FLASH on the Local Bus
108 #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
111 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
112 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
113 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
116 * PRIO1/PIGGY on the local bus CS1
123 #define CONFIG_SYS_NS16550_SERIAL
124 #define CONFIG_SYS_NS16550_REG_SIZE 1
125 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
127 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
128 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
131 * QE UEC ethernet configuration
133 #define CONFIG_UEC_ETH
134 #define CONFIG_ETHPRIME "UEC0"
136 #ifdef CONFIG_UEC_ETH1
137 #define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */
138 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
139 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK17
140 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
141 #define CONFIG_SYS_UEC1_PHY_ADDR 0
142 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
143 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
150 #ifndef CONFIG_SYS_RAMBOOT
151 #ifndef CONFIG_ENV_ADDR
152 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
153 CONFIG_SYS_MONITOR_LEN)
155 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
156 #ifndef CONFIG_ENV_OFFSET
157 #define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN)
160 /* Address and size of Redundant Environment Sector */
161 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
162 CONFIG_ENV_SECT_SIZE)
163 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
165 #else /* CFG_SYS_RAMBOOT */
166 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
167 #define CONFIG_ENV_SIZE 0x2000
168 #endif /* CFG_SYS_RAMBOOT */
171 #define CONFIG_SYS_I2C
172 #define CONFIG_SYS_NUM_I2C_BUSES 4
173 #define CONFIG_SYS_I2C_MAX_HOPS 1
174 #define CONFIG_SYS_I2C_FSL
175 #define CONFIG_SYS_FSL_I2C_SPEED 200000
176 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
177 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
178 #define CONFIG_SYS_I2C_OFFSET 0x3000
179 #define CONFIG_SYS_FSL_I2C2_SPEED 200000
180 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
181 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
182 #define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \
183 {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
184 {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
185 {1, {I2C_NULL_HOP} } }
187 #define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/
189 #if defined(CONFIG_CMD_NAND)
190 #define CONFIG_NAND_KMETER1
191 #define CONFIG_SYS_MAX_NAND_DEVICE 1
192 #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE
196 * For booting Linux, the board info and command line data
197 * have to be in the first 8 MB of memory, since this is
198 * the maximum mapped by the Linux kernel during initialization.
200 #define CONFIG_SYS_BOOTMAPSZ (8 << 20)
203 * Internal Definitions
205 #define BOOTFLASH_START 0xF0000000
207 #define CONFIG_KM_CONSOLE_TTY "ttyS0"
210 * Environment Configuration
212 #define CONFIG_ENV_OVERWRITE
213 #ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
214 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
217 #ifndef CONFIG_KM_DEF_ARCH
218 #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
221 #define CONFIG_EXTRA_ENV_SETTINGS \
225 "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \
226 "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \
230 #if defined(CONFIG_UEC_ETH)
231 #define CONFIG_HAS_ETH0
234 /* QE microcode/firmware address */
235 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
236 /* between the u-boot partition and env */
237 #ifndef CONFIG_SYS_QE_FW_ADDR
238 #define CONFIG_SYS_QE_FW_ADDR 0xF00C0000
244 /* 0x14000180 SICR_1 */
245 #define CONFIG_SYS_SICRL (0 \
246 | SICR_1_UART1_UART1RTS \
247 | SICR_1_I2C_CKSTOP \
250 | SICR_1_GPIO_A_GPIO \
251 | SICR_1_GPIO_B_GPIO \
252 | SICR_1_GPIO_C_GPIO \
253 | SICR_1_GPIO_D_GPIO \
254 | SICR_1_GPIO_E_GPIO \
255 | SICR_1_GPIO_F_GPIO \
256 | SICR_1_USB_A_UART2S \
257 | SICR_1_USB_B_UART2RTS \
262 /* 0x00080400 SICR_2 */
263 #define CONFIG_SYS_SICRH (0 \
265 | SICR_2_HDLC1_A_HDLC1 \
267 | SICR_2_ELBC_B_LCLK \
268 | SICR_2_HDLC2_A_HDLC2 \
269 | SICR_2_USB_D_GPIO \
271 | SICR_2_HDLC1_B_HDLC1 \
272 | SICR_2_HDLC1_C_HDLC1 \
273 | SICR_2_HDLC2_B_GPIO \
274 | SICR_2_HDLC2_C_HDLC2 \
279 #define CONFIG_SYS_GPR1 0x50008060
281 #define CONFIG_SYS_GP1DIR 0x00000000
282 #define CONFIG_SYS_GP1ODR 0x00000000
283 #define CONFIG_SYS_GP2DIR 0xFF000000
284 #define CONFIG_SYS_GP2ODR 0x00000000
286 #define CONFIG_SYS_DDRCDR (\
292 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
293 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
298 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
299 #define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
300 #define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
301 (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
303 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
304 CSCONFIG_ODT_RD_NEVER | \
305 CSCONFIG_ODT_WR_ONLY_CURRENT | \
306 CSCONFIG_ROW_BIT_13 | \
309 #define CONFIG_SYS_DDR_MODE 0x47860242
310 #define CONFIG_SYS_DDR_MODE2 0x8080c000
312 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
313 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
314 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
315 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
316 (0 << TIMING_CFG0_WWT_SHIFT) | \
317 (0 << TIMING_CFG0_RRT_SHIFT) | \
318 (0 << TIMING_CFG0_WRT_SHIFT) | \
319 (0 << TIMING_CFG0_RWT_SHIFT))
321 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
322 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
323 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
324 (3 << TIMING_CFG1_WRREC_SHIFT) | \
325 (7 << TIMING_CFG1_REFREC_SHIFT) | \
326 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
327 (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
328 (3 << TIMING_CFG1_PRETOACT_SHIFT))
330 #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
331 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
332 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
333 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
334 (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
335 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
336 (5 << TIMING_CFG2_CPO_SHIFT))
338 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
340 #define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
341 #define CONFIG_SYS_KMBEC_FPGA_SIZE 128
344 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
347 * Local Bus Configuration & Clock Setup
349 #define CONFIG_SYS_LBC_LBCR 0x00000000
351 /* must be after the include because KMBEC_FPGA is otherwise undefined */
352 #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
354 #define CONFIG_SYS_APP1_BASE 0xA0000000
355 #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */
356 #define CONFIG_SYS_APP2_BASE 0xB0000000
357 #define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */
360 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
363 * Init Local Bus Memory Controller:
365 * Bank Bus Machine PortSz Size Device
366 * ---- --- ------- ------ ----- ------
367 * 2 Local UPMA 16 bit 256MB APP1
368 * 3 Local GPCM 16 bit 256MB APP2
373 /* ethernet port connected to piggy (UEC2) */
374 #define CONFIG_HAS_ETH1
375 #define CONFIG_UEC_ETH2
376 #define CONFIG_SYS_UEC2_UCC_NUM 2 /* UCC3 */
377 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
378 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK12
379 #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
380 #define CONFIG_SYS_UEC2_PHY_ADDR 0
381 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
382 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
384 #endif /* __CONFIG_H */