include/configs/kmsupx5.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   4  *                    Dave Liu <daveliu@freescale.com>
   5  *
   6  * Copyright (C) 2007 Logic Product Development, Inc.
   7  *                    Peter Barada <peterb@logicpd.com>
   8  *
   9  * Copyright (C) 2007 MontaVista Software, Inc.
  10  *                    Anton Vorontsov <avorontsov@ru.mvista.com>
  11  *
  12  * (C) Copyright 2008
  13  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  14  *
  15  * (C) Copyright 2010-2013
  16  * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com
  17  * Holger Brunck,  Keymile GmbH, holger.bruncl@keymile.com
  18  */
  19
  20 #ifndef __CONFIG_H
  21 #define __CONFIG_H
  22
  23 /*
  24  * High Level Configuration Options
  25  */
  26 #define CONFIG_KM_BOARD_NAME    "kmsupx5"
  27 #define CONFIG_HOSTNAME         "kmsupx5"
  28
  29 /*
  30  * High Level Configuration Options
  31  */
  32 #define CONFIG_QE       /* Has QE */
  33 #define CONFIG_KM8321   /* Keymile PBEC8321 board specific */
  34
  35 #define CONFIG_KM_DEF_ARCH      "arch=ppc_8xx\0"
  36
  37 /* include common defines/options for all 83xx Keymile boards */
  38 #include "km83xx-common.h"
  39
  40 /*
  41  * System IO Config
  42  */
  43 #define CONFIG_SYS_SICRL        SICRL_IRQ_CKS
  44
  45 /*
  46  * Hardware Reset Configuration Word
  47  */
  48 #define CONFIG_SYS_HRCW_LOW (\
  49         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
  50         HRCWL_DDR_TO_SCB_CLK_2X1 | \
  51         HRCWL_CSB_TO_CLKIN_2X1 | \
  52         HRCWL_CORE_TO_CSB_2_5X1 | \
  53         HRCWL_CE_PLL_VCO_DIV_2 | \
  54         HRCWL_CE_TO_PLL_1X3)
  55
  56 #define CONFIG_SYS_HRCW_HIGH (\
  57         HRCWH_PCI_AGENT | \
  58         HRCWH_PCI_ARBITER_DISABLE | \
  59         HRCWH_CORE_ENABLE | \
  60         HRCWH_FROM_0X00000100 | \
  61         HRCWH_BOOTSEQ_DISABLE | \
  62         HRCWH_SW_WATCHDOG_DISABLE | \
  63         HRCWH_ROM_LOC_LOCAL_16BIT | \
  64         HRCWH_BIG_ENDIAN | \
  65         HRCWH_LALE_NORMAL)
  66
  67 #define CONFIG_SYS_DDRCDR (\
  68         DDRCDR_EN | \
  69         DDRCDR_PZ_MAXZ | \
  70         DDRCDR_NZ_MAXZ | \
  71         DDRCDR_M_ODR)
  72
  73 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000007f
  74 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
  75                                          SDRAM_CFG_32_BE | \
  76                                          SDRAM_CFG_SREN | \
  77                                          SDRAM_CFG_HSE)
  78
  79 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
  80 #define CONFIG_SYS_DDR_CLK_CNTL         (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  81 #define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
  82                                  (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
  83
  84 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN | CSCONFIG_AP | \
  85                                          CSCONFIG_ODT_WR_CFG | \
  86                                          CSCONFIG_ROW_BIT_13 | \
  87                                          CSCONFIG_COL_BIT_10)
  88
  89 #define CONFIG_SYS_DDR_MODE     0x47860242
  90 #define CONFIG_SYS_DDR_MODE2    0x8080c000
  91
  92 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
  93                                  (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
  94                                  (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
  95                                  (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
  96                                  (0 << TIMING_CFG0_WWT_SHIFT) | \
  97                                  (0 << TIMING_CFG0_RRT_SHIFT) | \
  98                                  (0 << TIMING_CFG0_WRT_SHIFT) | \
  99                                  (0 << TIMING_CFG0_RWT_SHIFT))
 100
 101 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
 102                                  (2 << TIMING_CFG1_WRTORD_SHIFT) | \
 103                                  (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
 104                                  (3 << TIMING_CFG1_WRREC_SHIFT) | \
 105                                  (7 << TIMING_CFG1_REFREC_SHIFT) | \
 106                                  (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
 107                                  (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
 108                                  (3 << TIMING_CFG1_PRETOACT_SHIFT))
 109
 110 #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
 111                                  (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
 112                                  (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
 113                                  (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
 114                                  (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
 115                                  (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
 116                                  (5 << TIMING_CFG2_CPO_SHIFT))
 117
 118 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 119
 120 #define CONFIG_SYS_KMBEC_FPGA_BASE      0xE8000000
 121 #define CONFIG_SYS_KMBEC_FPGA_SIZE      128
 122
 123 /* EEprom support */
 124 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 125
 126 /*
 127  * Local Bus Configuration & Clock Setup
 128  */
 129 #define CONFIG_SYS_LCRR_DBYP    0x80000000
 130 #define CONFIG_SYS_LCRR_EADC    0x00010000
 131 #define CONFIG_SYS_LCRR_CLKDIV  0x00000002
 132
 133 #define CONFIG_SYS_LBC_LBCR     0x00000000
 134
 135 /*
 136  * MMU Setup
 137  */
 138 #define CONFIG_SYS_IBAT7L       (0)
 139 #define CONFIG_SYS_IBAT7U       (0)
 140 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 141 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 142
 143 #define CONFIG_SYS_APP1_BASE    0xA0000000    /* PAXG */
 144 #define CONFIG_SYS_APP1_SIZE    256 /* Megabytes */
 145
 146 /*
 147  * Init Local Bus Memory Controller:
 148  *                                    Device on board
 149  * Bank Bus     Machine PortSz Size   TUDA1  TUXA1  TUGE1   KMSUPX4 KMOPTI2
 150  * -----------------------------------------------------------------------------
 151  *  2   Local   GPCM    8 bit  256MB  PAXG   LPXF   PAXI    LPXF    PAXE
 152  *  3   Local   GPCM    8 bit  256MB  PINC3  PINC2  unused  unused  OPI2(16 bit)
 153  *
 154  *                                    Device on board (continued)
 155  * Bank Bus     Machine PortSz Size   KMTEPR2
 156  * -----------------------------------------------------------------------------
 157  *  2   Local   GPCM    8 bit  256MB  NVRAM
 158  *  3   Local   GPCM    8 bit  256MB  TEP2 (16 bit)
 159  */
 160
 161 /*
 162  * Configuration for C2 on the local bus
 163  */
 164 /* Window base at flash base */
 165 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_APP1_BASE
 166 /* Window size: 256 MB */
 167 #define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_256MB)
 168
 169 #define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_APP1_BASE | \
 170                                  BR_PS_8 | \
 171                                  BR_MS_GPCM | \
 172                                  BR_V)
 173
 174 #define CONFIG_SYS_OR2_PRELIM   (MEG_TO_AM(CONFIG_SYS_APP1_SIZE) | \
 175                                  OR_GPCM_CSNT | \
 176                                  OR_GPCM_ACS_DIV4 | \
 177                                  OR_GPCM_SCY_2 | \
 178                                  OR_GPCM_TRLX_SET | \
 179                                  OR_GPCM_EHTR_CLEAR | \
 180                                  OR_GPCM_EAD)
 181
 182 /*
 183  * MMU Setup
 184  */
 185 /* APP1: icache cacheable, but dcache-inhibit and guarded */
 186 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_APP1_BASE | \
 187                                  BATL_PP_RW | \
 188                                  BATL_MEMCOHERENCE)
 189 /* 512M should also include APP2... */
 190 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_APP1_BASE | \
 191                                  BATU_BL_256M | \
 192                                  BATU_VS | \
 193                                  BATU_VP)
 194 #define CONFIG_SYS_DBAT5L       (CONFIG_SYS_APP1_BASE | \
 195                                  BATL_PP_RW | \
 196                                  BATL_CACHEINHIBIT | \
 197                                  BATL_GUARDEDSTORAGE)
 198 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 199
 200 #define CONFIG_SYS_IBAT6L       (0)
 201 #define CONFIG_SYS_IBAT6U       (0)
 202 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 203 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 204
 205 #define CONFIG_SYS_IBAT7L       (0)
 206 #define CONFIG_SYS_IBAT7U       (0)
 207 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 208 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 209
 210 #endif /* __CONFIG_H */