1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2013 Keymile AG
4 * Valentin Longchamp <valentin.longchamp@keymile.com>
10 #if defined(CONFIG_KMCOGE4)
11 #define CONFIG_HOSTNAME "kmcoge4"
12 #define CONFIG_KM_BOARD_NAME "kmcoge4"
15 #error ("Board not supported")
18 #define CONFIG_KMP204X
20 #define CONFIG_KM_DEF_NETDEV "netdev=eth0\0"
22 /* an additionnal option is required for UBI as subpage access is
25 #define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048"
27 #define CONFIG_NAND_ECC_BCH
29 /* common KM defines */
30 #include "km/keymile-common.h"
32 #define CONFIG_SYS_RAMBOOT
33 #define CONFIG_RAMBOOT_PBL
34 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
35 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
36 #define CONFIG_SYS_FSL_PBL_PBI board/keymile/kmp204x/pbi.cfg
37 #define CONFIG_SYS_FSL_PBL_RCW board/keymile/kmp204x/rcw_kmp204x.cfg
39 /* High Level Configuration Options */
40 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
41 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
43 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
44 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
45 #define CONFIG_PCIE1 /* PCIE controller 1 */
46 #define CONFIG_PCIE3 /* PCIE controller 3 */
47 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
48 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
50 #define CONFIG_SYS_DPAA_RMAN /* RMan */
52 /* Environment in SPI Flash */
53 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB for u-boot */
54 #define CONFIG_ENV_SIZE 0x004000 /* 16K env */
55 #define CONFIG_ENV_SECT_SIZE 0x010000
56 #define CONFIG_ENV_OFFSET_REDUND 0x110000
57 #define CONFIG_ENV_TOTAL_SIZE 0x020000
60 unsigned long get_board_sys_clk(unsigned long dummy);
62 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
65 * These can be toggled for performance analysis, otherwise use default.
67 #define CONFIG_SYS_CACHE_STASHING
68 #define CONFIG_BACKSIDE_L2_CACHE
69 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
70 #define CONFIG_BTB /* toggle branch predition */
72 #define CONFIG_ENABLE_36BIT_PHYS
74 #define CONFIG_ADDR_MAP
75 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
77 #define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS /* POST memory regions test */
80 * Config the L3 Cache as L3 SRAM
82 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
83 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \
84 CONFIG_RAMBOOT_TEXT_BASE)
85 #define CONFIG_SYS_L3_SIZE (1024 << 10)
86 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
88 #define CONFIG_SYS_DCSRBAR 0xf0000000
89 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
94 #define CONFIG_VERY_BIG_RAM
95 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
96 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
98 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
99 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
101 #define CONFIG_DDR_SPD
103 #define CONFIG_SYS_SPD_BUS_NUM 0
104 #define SPD_EEPROM_ADDRESS 0x54
105 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
107 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
108 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
110 /******************************************************************************
112 * ... -------------------------------------------------------
113 * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM
114 * ... |<------------------- pram -------------------------->|
115 * ... -------------------------------------------------------
117 * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose
118 * @CONFIG_KM_PHRAM: address for /var
119 * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application)
120 * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM
123 /* size of rootfs in RAM */
124 #define CONFIG_KM_ROOTFSSIZE 0x0
125 /* pseudo-non volatile RAM [hex] */
126 #define CONFIG_KM_PNVRAM 0x80000
127 /* physical RAM MTD size [hex] */
128 #define CONFIG_KM_PHRAM 0x100000
129 /* reserved pram area at the end of memory [hex]
130 * u-boot reserves some memory for the MP boot page
132 #define CONFIG_KM_RESERVED_PRAM 0x1000
133 /* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable
134 * is not valid yet, which is the case for when u-boot copies itself to RAM
136 #define CONFIG_PRAM ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM) >> 10)
138 #define CONFIG_KM_CRAMFS_ADDR 0x2000000
139 #define CONFIG_KM_KERNEL_ADDR 0x1000000 /* max kernel size 15.5Mbytes */
140 #define CONFIG_KM_FDT_ADDR 0x1F80000 /* max dtb size 0.5Mbytes */
143 * Local Bus Definitions
146 /* Set the local bus clock 1/8 of plat clk, 2 clk delay LALE */
147 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_2)
150 #define CONFIG_NAND_FSL_ELBC
151 #define CONFIG_SYS_NAND_BASE 0xffa00000
152 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
154 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
155 #define CONFIG_SYS_MAX_NAND_DEVICE 1
156 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
158 /* NAND flash config */
159 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
160 | BR_PS_8 /* Port Size = 8 bit */ \
161 | BR_MS_FCM /* MSEL = FCM */ \
164 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB /* length 256K */ \
165 | OR_FCM_BCTLD /* LBCTL not ass */ \
166 | OR_FCM_SCY_1 /* 1 clk wait cycle */ \
167 | OR_FCM_RST /* 1 clk read setup */ \
168 | OR_FCM_PGS /* Large page size */ \
169 | OR_FCM_CST) /* 0.25 command setup */
171 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
172 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
175 #define CONFIG_SYS_QRIO_BASE 0xfb000000
176 #define CONFIG_SYS_QRIO_BASE_PHYS 0xffb000000ull
178 #define CONFIG_SYS_QRIO_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE_PHYS) \
179 | BR_PS_8 /* Port Size 8 bits */ \
180 | BR_DECC_OFF /* no error corr */ \
181 | BR_MS_GPCM /* MSEL = GPCM */ \
184 #define CONFIG_SYS_QRIO_OR_PRELIM (OR_AM_64KB /* length 64K */ \
185 | OR_GPCM_BCTLD /* no LCTL assert */ \
186 | OR_GPCM_ACS_DIV4 /* LCS 1/4 clk after */ \
187 | OR_GPCM_SCY_2 /* 2 clk wait cycles */ \
188 | OR_GPCM_TRLX /* relaxed tmgs */ \
189 | OR_GPCM_EAD) /* extra bus clk cycles */
191 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_QRIO_BR_PRELIM /* QRIO Base Address */
192 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_QRIO_OR_PRELIM /* QRIO Options */
194 #define CONFIG_MISC_INIT_F
196 #define CONFIG_HWCONFIG
198 /* define to use L1 as initial stack */
199 #define CONFIG_L1_INIT_RAM
200 #define CONFIG_SYS_INIT_RAM_LOCK
201 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
202 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
203 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
204 /* The assembler doesn't like typecast */
205 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
206 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
207 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
208 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
210 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
211 GENERATED_GBL_DATA_SIZE)
212 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
214 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
215 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
216 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
218 /* Serial Port - controlled on board with jumper J8
222 #define CONFIG_SYS_NS16550_SERIAL
223 #define CONFIG_SYS_NS16550_REG_SIZE 1
224 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
226 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x11C500)
227 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x11C600)
228 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR + 0x11D500)
229 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR + 0x11D600)
231 #define CONFIG_KM_CONSOLE_TTY "ttyS0"
235 #define CONFIG_SYS_I2C
236 #define CONFIG_SYS_I2C_INIT_BOARD
237 #define CONFIG_SYS_I2C_SPEED 100000 /* deblocking */
238 #define CONFIG_SYS_NUM_I2C_BUSES 3
239 #define CONFIG_SYS_I2C_MAX_HOPS 1
240 #define CONFIG_SYS_I2C_FSL /* Use FSL I2C driver */
241 #define CONFIG_I2C_MULTI_BUS
242 #define CONFIG_I2C_CMD_TREE
243 #define CONFIG_SYS_FSL_I2C_SPEED 400000
244 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
245 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
246 #define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \
247 {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \
248 {0, {{I2C_MUX_PCA9547, 0x70, 2 } } }, \
251 void set_sda(int state);
252 void set_scl(int state);
257 #define CONFIG_KM_IVM_BUS 1 /* I2C1 (Mux-Port 1)*/
260 * eSPI - Enhanced SPI
265 * Memory space is mapped 1-1, but I/O space must start from 0.
268 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
269 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
270 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
271 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
272 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
273 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
274 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
275 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
276 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
278 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
279 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
280 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
281 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
282 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
283 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8010000
284 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
285 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8010000ull
286 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
289 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
290 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
291 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
292 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
293 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
294 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
295 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
296 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
297 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
298 CONFIG_SYS_BMAN_CENA_SIZE)
299 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
300 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
301 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
302 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
303 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
304 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
305 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
306 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
307 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
308 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
309 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
310 CONFIG_SYS_QMAN_CENA_SIZE)
311 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
312 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
314 #define CONFIG_SYS_DPAA_FMAN
315 #define CONFIG_SYS_DPAA_PME
316 /* Default address of microcode for the Linux Fman driver
317 * env is stored at 0x100000, sector size is 0x10000, x2 (redundant)
318 * ucode is stored after env, so we got 0x120000.
320 #define CONFIG_SYS_FMAN_FW_ADDR 0x120000
321 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
322 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
324 #define CONFIG_PHYLIB_10G
326 #define CONFIG_PCI_INDIRECT_BRIDGE
328 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
330 /* RGMII (FM1@DTESC5) is used as debug itf, it's the only one configured */
331 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x11
332 #define CONFIG_SYS_TBIPA_VALUE 8
333 #define CONFIG_ETHPRIME "FM1@DTSEC5"
338 #define CONFIG_LOADS_ECHO /* echo on for serial download */
339 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
344 #define CONFIG_WATCHDOG /* enable CPU watchdog */
345 #define CONFIG_WATCHDOG_PRESC 34 /* wdog prescaler 2^(64-34) (~10min) */
346 #define CONFIG_WATCHDOG_RC WRC_CHIP /* reset chip on watchdog event */
349 * additionnal command line configuration.
352 /* we don't need flash support */
353 #undef CONFIG_JFFS2_CMDLINE
356 * For booting Linux, the board info and command line data
357 * have to be in the first 64 MB of memory, since this is
358 * the maximum mapped by the Linux kernel during initialization.
360 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */
361 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
363 #ifdef CONFIG_CMD_KGDB
364 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
367 #define __USB_PHY_TYPE utmi
368 #define CONFIG_USB_EHCI_FSL
371 * Environment Configuration
373 #define CONFIG_ENV_OVERWRITE
374 #ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
375 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
378 /* architecture specific default bootargs */
379 #define CONFIG_KM_DEF_BOOT_ARGS_CPU ""
381 /* FIXME: FDT_ADDR is unspecified */
382 #define CONFIG_KM_DEF_ENV_CPU \
383 "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \
385 "cramfsload ${fdt_addr_r} " \
386 "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \
387 "fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0" \
388 "u-boot=" CONFIG_HOSTNAME "/u-boot.pbl\0" \
390 "sf probe 0;sf erase 0 +${filesize};" \
391 "sf write ${load_addr_r} 0 ${filesize};\0" \
392 "set_fdthigh=true\0" \
396 #define CONFIG_HW_ENV_SETTINGS \
397 "hwconfig=fsl_ddr:ctlr_intlv=cacheline\0" \
398 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
401 #define CONFIG_KM_NEW_ENV \
402 "newenv=sf probe 0;" \
403 "sf erase " __stringify(CONFIG_ENV_OFFSET) " " \
404 __stringify(CONFIG_ENV_TOTAL_SIZE)"\0"
406 /* ppc_82xx is the equivalent to ppc_6xx, the generic ppc toolchain */
407 #ifndef CONFIG_KM_DEF_ARCH
408 #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
411 #define CONFIG_EXTRA_ENV_SETTINGS \
415 CONFIG_HW_ENV_SETTINGS \
416 "EEprom_ivm=pca9547:70:9\0" \
420 #define CONFIG_SYS_LBAPP2_BASE 0xE0000000
421 #define CONFIG_SYS_LBAPP2_BASE_PHYS 0xFE0000000ull
423 #define CONFIG_SYS_LBAPP2_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_LBAPP2_BASE_PHYS) \
424 | BR_PS_8 /* Port Size 8 bits */ \
425 | BR_DECC_OFF /* no error corr */ \
426 | BR_MS_GPCM /* MSEL = GPCM */ \
429 #define CONFIG_SYS_LBAPP2_OR_PRELIM (OR_AM_256MB /* length 256MB */ \
430 | OR_GPCM_ACS_DIV2 /* LCS 1/2 clk after */ \
431 | OR_GPCM_CSNT /* LCS 1/4 clk before */ \
432 | OR_GPCM_SCY_2 /* 2 clk wait cycles */ \
433 | OR_GPCM_TRLX /* relaxed tmgs */ \
434 | OR_GPCM_EAD) /* extra bus clk cycles */
435 /* Local bus app2 Base Address */
436 #define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_LBAPP2_BR_PRELIM
437 /* Local bus app2 Options */
438 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_LBAPP2_OR_PRELIM
440 #endif /* __CONFIG_H */