1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Holger Brunck, Keymile GmbH Hannover, <holger.brunck@keymile.com>
5 * Christian Herzig, Keymile AG Switzerland, <christian.herzig@keymile.com>
11 /* KMBEC FPGA (PRIO) */
12 #define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
13 #define CONFIG_SYS_KMBEC_FPGA_SIZE 64
15 #define CONFIG_HOSTNAME "kmcoge5ne"
16 #define CONFIG_KM_BOARD_NAME "kmcoge5ne"
17 #define CONFIG_KM_DEF_NETDEV "netdev=eth1\0"
18 #define CONFIG_NAND_ECC_BCH
19 #define CONFIG_NAND_KMETER1
20 #define CONFIG_SYS_MAX_NAND_DEVICE 1
21 #define NAND_MAX_CHIPS 1
22 #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
24 #define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0"
25 #define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1"
28 * High Level Configuration Options
30 #define CONFIG_QE /* Has QE */
32 /* include common defines/options for all Keymile boards */
33 #include "km/keymile-common.h"
34 #include "km/km-powerpc.h"
39 #define CONFIG_83XX_CLKIN 66000000
40 #define CONFIG_SYS_CLK_FREQ 66000000
41 #define CONFIG_83XX_PCICLK 66000000
46 #define CONFIG_SYS_IMMR 0xE0000000
49 * Bus Arbitration Configuration Register (ACR)
51 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */
52 #define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */
53 #define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */
54 #define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */
59 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
60 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
61 #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
63 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
64 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
65 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
67 #define CFG_83XX_DDR_USES_CS0
70 * Manually set up DDR parameters
73 #define CONFIG_SYS_DDR_SIZE 2048 /* MB */
78 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
79 #define CONFIG_SYS_FLASH_BASE 0xF0000000
81 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
82 #define CONFIG_SYS_RAMBOOT
85 /* Reserve 768 kB for Mon */
86 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
89 * Initial RAM Base Address Setup
91 #define CONFIG_SYS_INIT_RAM_LOCK
92 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
93 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */
94 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
95 GENERATED_GBL_DATA_SIZE)
98 * Init Local Bus Memory Controller:
100 * Bank Bus Machine PortSz Size Device
101 * ---- --- ------- ------ ----- ------
102 * 0 Local GPCM 16 bit 256MB FLASH
103 * 1 Local GPCM 8 bit 128MB GPIO/PIGGY
107 * FLASH on the Local Bus
109 #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
112 #define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V)
113 #define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
115 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
116 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
117 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
120 * PRIO1/PIGGY on the local bus CS1
124 #define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V)
125 #define CONFIG_SYS_OR1_PRELIM (OR_AM_64MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
130 #define CONFIG_SYS_NS16550_SERIAL
131 #define CONFIG_SYS_NS16550_REG_SIZE 1
132 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
134 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
135 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
138 * QE UEC ethernet configuration
140 #define CONFIG_UEC_ETH
141 #define CONFIG_ETHPRIME "UEC0"
143 #define CONFIG_UEC_ETH1 /* GETH1 */
144 #define UEC_VERBOSE_DEBUG 1
146 #ifdef CONFIG_UEC_ETH1
147 #define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */
148 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
149 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK17
150 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
151 #define CONFIG_SYS_UEC1_PHY_ADDR 0
152 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
153 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
160 #ifndef CONFIG_SYS_RAMBOOT
161 #ifndef CONFIG_ENV_ADDR
162 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
163 CONFIG_SYS_MONITOR_LEN)
165 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
166 #ifndef CONFIG_ENV_OFFSET
167 #define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN)
170 /* Address and size of Redundant Environment Sector */
171 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
172 CONFIG_ENV_SECT_SIZE)
173 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
175 #else /* CFG_SYS_RAMBOOT */
176 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
177 #define CONFIG_ENV_SIZE 0x2000
178 #endif /* CFG_SYS_RAMBOOT */
181 #define CONFIG_SYS_I2C
182 #define CONFIG_SYS_NUM_I2C_BUSES 4
183 #define CONFIG_SYS_I2C_MAX_HOPS 1
184 #define CONFIG_SYS_I2C_FSL
185 #define CONFIG_SYS_FSL_I2C_SPEED 200000
186 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
187 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
188 #define CONFIG_SYS_I2C_OFFSET 0x3000
189 #define CONFIG_SYS_FSL_I2C2_SPEED 200000
190 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
191 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
192 #define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \
193 {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
194 {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
195 {1, {I2C_NULL_HOP} } }
197 #define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/
199 #if defined(CONFIG_CMD_NAND)
200 #define CONFIG_NAND_KMETER1
201 #define CONFIG_SYS_MAX_NAND_DEVICE 1
202 #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE
206 * For booting Linux, the board info and command line data
207 * have to be in the first 8 MB of memory, since this is
208 * the maximum mapped by the Linux kernel during initialization.
210 #define CONFIG_SYS_BOOTMAPSZ (8 << 20)
215 #define CONFIG_SYS_HID0_INIT 0x000000000
216 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
217 HID0_ENABLE_INSTRUCTION_CACHE)
218 #define CONFIG_SYS_HID2 HID2_HBE
221 * Internal Definitions
223 #define BOOTFLASH_START 0xF0000000
225 #define CONFIG_KM_CONSOLE_TTY "ttyS0"
228 * Environment Configuration
230 #define CONFIG_ENV_OVERWRITE
231 #ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
232 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
235 #ifndef CONFIG_KM_DEF_ARCH
236 #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
239 #define CONFIG_EXTRA_ENV_SETTINGS \
243 "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \
244 "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \
248 #if defined(CONFIG_UEC_ETH)
249 #define CONFIG_HAS_ETH0
255 #define CONFIG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI)
260 #define CONFIG_SYS_DDR_SDRAM_CFG (\
261 SDRAM_CFG_SDRAM_TYPE_DDR2 | \
265 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
268 * KMCOGE5NE has 512 MB RAM
270 #define CONFIG_SYS_DDR_CS0_CONFIG (\
273 CSCONFIG_ODT_WR_ONLY_CURRENT | \
274 CSCONFIG_BANK_BIT_3 | \
275 CSCONFIG_ROW_BIT_13 | \
278 #define CONFIG_SYS_DDR_CLK_CNTL (\
279 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
281 #define CONFIG_SYS_DDR_INTERVAL (\
282 (0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
283 (0x203 << SDRAM_INTERVAL_REFINT_SHIFT))
285 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
287 #define CONFIG_SYS_DDRCDR (\
290 #define CONFIG_SYS_DDR_MODE 0x47860452
291 #define CONFIG_SYS_DDR_MODE2 0x8080c000
293 #define CONFIG_SYS_DDR_TIMING_0 (\
294 (2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
295 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
296 (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
297 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
298 (0 << TIMING_CFG0_WWT_SHIFT) | \
299 (0 << TIMING_CFG0_RRT_SHIFT) | \
300 (0 << TIMING_CFG0_WRT_SHIFT) | \
301 (0 << TIMING_CFG0_RWT_SHIFT))
303 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \
304 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
305 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
306 (3 << TIMING_CFG1_WRREC_SHIFT) | \
307 (7 << TIMING_CFG1_REFREC_SHIFT) | \
308 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
309 (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
310 (3 << TIMING_CFG1_PRETOACT_SHIFT))
312 #define CONFIG_SYS_DDR_TIMING_2 (\
313 (0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \
314 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
315 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
316 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
317 (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
318 (5 << TIMING_CFG2_CPO_SHIFT) | \
319 (0 << TIMING_CFG2_ADD_LAT_SHIFT))
321 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
324 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
327 * Local Bus Configuration & Clock Setup
329 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
330 #define CONFIG_SYS_LCRR_EADC LCRR_EADC_2
331 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
334 * PAXE on the local bus CS3
336 #define CONFIG_SYS_PAXE_BASE 0xA0000000
337 #define CONFIG_SYS_PAXE_SIZE 256
340 #define CONFIG_SYS_BR3_PRELIM (0xA0000000 | BR_PS_8 | BR_V)
341 #define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
344 * BFTIC3 on the local bus CS4
346 #define CONFIG_SYS_BFTIC3_BASE 0xB0000000
347 #define CONFIG_SYS_BFTIC3_SIZE 256
350 #define CONFIG_SYS_BR4_PRELIM (0xB0000000 | BR_PS_8 | BR_V)
351 #define CONFIG_SYS_OR4_PRELIM (OR_AM_256MB| OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
353 /* enable POST tests */
354 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS)
355 #define CONFIG_POST_EXTERNAL_WORD_FUNCS /* use own functions, not generic */
356 #define CPM_POST_WORD_ADDR CONFIG_SYS_MEMTEST_END
357 #define CONFIG_TESTPIN_REG gprt3 /* for kmcoge5ne */
358 #define CONFIG_TESTPIN_MASK 0x20 /* for kmcoge5ne */