include/configs/kmcoge5ne.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2012
   4  * Holger Brunck, Keymile GmbH Hannover, <holger.brunck@keymile.com>
   5  * Christian Herzig, Keymile AG Switzerland, <christian.herzig@keymile.com>
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 /* KMBEC FPGA (PRIO) */
  12 #define CONFIG_SYS_KMBEC_FPGA_BASE      0xE8000000
  13 #define CONFIG_SYS_KMBEC_FPGA_SIZE      64
  14
  15 #define CONFIG_HOSTNAME         "kmcoge5ne"
  16 #define CONFIG_KM_BOARD_NAME    "kmcoge5ne"
  17 #define CONFIG_KM_DEF_NETDEV    "netdev=eth1\0"
  18 #define CONFIG_NAND_ECC_BCH
  19 #define CONFIG_NAND_KMETER1
  20 #define CONFIG_SYS_MAX_NAND_DEVICE              1
  21 #define NAND_MAX_CHIPS                          1
  22 #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
  23
  24 #define CONFIG_KM_UBI_PARTITION_NAME_BOOT       "ubi0"
  25 #define CONFIG_KM_UBI_PARTITION_NAME_APP        "ubi1"
  26
  27 /*
  28  * High Level Configuration Options
  29  */
  30 #define CONFIG_QE                       /* Has QE */
  31
  32 /* include common defines/options for all Keymile boards */
  33 #include "km/keymile-common.h"
  34 #include "km/km-powerpc.h"
  35
  36 /*
  37  * System Clock Setup
  38  */
  39 #define CONFIG_83XX_CLKIN               66000000
  40 #define CONFIG_SYS_CLK_FREQ             66000000
  41 #define CONFIG_83XX_PCICLK              66000000
  42
  43 /*
  44  * IMMR new address
  45  */
  46 #define CONFIG_SYS_IMMR         0xE0000000
  47
  48 /*
  49  * Bus Arbitration Configuration Register (ACR)
  50  */
  51 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* pipeline depth 4 transactions */
  52 #define CONFIG_SYS_ACR_RPTCNT   3       /* 4 consecutive transactions */
  53 #define CONFIG_SYS_ACR_APARK    0       /* park bus to master (below) */
  54 #define CONFIG_SYS_ACR_PARKM    3       /* parking master = QuiccEngine */
  55
  56 /*
  57  * DDR Setup
  58  */
  59 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
  60 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  61 #define CONFIG_SYS_SDRAM_BASE2  (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
  62
  63 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  64 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN | \
  65                                         DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  66
  67 #define CFG_83XX_DDR_USES_CS0
  68
  69 /*
  70  * Manually set up DDR parameters
  71  */
  72 #define CONFIG_DDR_II
  73 #define CONFIG_SYS_DDR_SIZE             2048 /* MB */
  74
  75 /*
  76  * The reserved memory
  77  */
  78 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  79 #define CONFIG_SYS_FLASH_BASE           0xF0000000
  80
  81 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  82 #define CONFIG_SYS_RAMBOOT
  83 #endif
  84
  85 /* Reserve 768 kB for Mon */
  86 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
  87
  88 /*
  89  * Initial RAM Base Address Setup
  90  */
  91 #define CONFIG_SYS_INIT_RAM_LOCK
  92 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
  93 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* End of used area in RAM */
  94 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
  95                                                 GENERATED_GBL_DATA_SIZE)
  96
  97 /*
  98  * Init Local Bus Memory Controller:
  99  *
 100  * Bank Bus     Machine PortSz  Size  Device
 101  * ---- ---     ------- ------  -----  ------
 102  *  0   Local   GPCM    16 bit  256MB FLASH
 103  *  1   Local   GPCM     8 bit  128MB GPIO/PIGGY
 104  *
 105  */
 106 /*
 107  * FLASH on the Local Bus
 108  */
 109 #define CONFIG_SYS_FLASH_SIZE           256 /* max FLASH size is 256M */
 110
 111 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 112 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_256MB)
 113
 114 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE | \
 115                                 BR_PS_16 | /* 16 bit port size */ \
 116                                 BR_MS_GPCM | /* MSEL = GPCM */ \
 117                                 BR_V)
 118
 119 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
 120                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 121                                 OR_GPCM_SCY_5 | \
 122                                 OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 123
 124 #define CONFIG_SYS_MAX_FLASH_BANKS      1   /* max num of flash banks   */
 125 #define CONFIG_SYS_MAX_FLASH_SECT       512 /* max num of sects on one chip */
 126 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
 127
 128 /*
 129  * PRIO1/PIGGY on the local bus CS1
 130  */
 131 /* Window base at flash base */
 132 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_KMBEC_FPGA_BASE
 133 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_128MB)
 134
 135 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_KMBEC_FPGA_BASE | \
 136                                 BR_PS_8 | /* 8 bit port size */ \
 137                                 BR_MS_GPCM | /* MSEL = GPCM */ \
 138                                 BR_V)
 139 #define CONFIG_SYS_OR1_PRELIM   (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \
 140                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 141                                 OR_GPCM_SCY_2 | \
 142                                 OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 143
 144 /*
 145  * Serial Port
 146  */
 147 #define CONFIG_SYS_NS16550_SERIAL
 148 #define CONFIG_SYS_NS16550_REG_SIZE     1
 149 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 150
 151 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 152 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 153
 154 /*
 155  * QE UEC ethernet configuration
 156  */
 157 #define CONFIG_UEC_ETH
 158 #define CONFIG_ETHPRIME         "UEC0"
 159
 160 #define CONFIG_UEC_ETH1         /* GETH1 */
 161 #define UEC_VERBOSE_DEBUG       1
 162
 163 #ifdef CONFIG_UEC_ETH1
 164 #define CONFIG_SYS_UEC1_UCC_NUM 3       /* UCC4 */
 165 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK_NONE /* not used in RMII Mode */
 166 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK17
 167 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 168 #define CONFIG_SYS_UEC1_PHY_ADDR        0
 169 #define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_RMII
 170 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 171 #endif
 172
 173 /*
 174  * Environment
 175  */
 176
 177 #ifndef CONFIG_SYS_RAMBOOT
 178 #ifndef CONFIG_ENV_ADDR
 179 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 180                                         CONFIG_SYS_MONITOR_LEN)
 181 #endif
 182 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 183 #ifndef CONFIG_ENV_OFFSET
 184 #define CONFIG_ENV_OFFSET       (CONFIG_SYS_MONITOR_LEN)
 185 #endif
 186
 187 /* Address and size of Redundant Environment Sector     */
 188 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + \
 189                                                 CONFIG_ENV_SECT_SIZE)
 190 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 191
 192 #else /* CFG_SYS_RAMBOOT */
 193 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 194 #define CONFIG_ENV_SIZE         0x2000
 195 #endif /* CFG_SYS_RAMBOOT */
 196
 197 /* I2C */
 198 #define CONFIG_SYS_I2C
 199 #define CONFIG_SYS_NUM_I2C_BUSES        4
 200 #define CONFIG_SYS_I2C_MAX_HOPS         1
 201 #define CONFIG_SYS_I2C_FSL
 202 #define CONFIG_SYS_FSL_I2C_SPEED        200000
 203 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 204 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 205 #define CONFIG_SYS_I2C_OFFSET           0x3000
 206 #define CONFIG_SYS_FSL_I2C2_SPEED       200000
 207 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 208 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 209 #define CONFIG_SYS_I2C_BUSES    {{0, {I2C_NULL_HOP} }, \
 210                 {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
 211                 {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
 212                 {1, {I2C_NULL_HOP} } }
 213
 214 #define CONFIG_KM_IVM_BUS               2       /* I2C2 (Mux-Port 1)*/
 215
 216 #if defined(CONFIG_CMD_NAND)
 217 #define CONFIG_NAND_KMETER1
 218 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 219 #define CONFIG_SYS_NAND_BASE            CONFIG_SYS_KMBEC_FPGA_BASE
 220 #endif
 221
 222 /*
 223  * For booting Linux, the board info and command line data
 224  * have to be in the first 8 MB of memory, since this is
 225  * the maximum mapped by the Linux kernel during initialization.
 226  */
 227 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)
 228
 229 /*
 230  * Core HID Setup
 231  */
 232 #define CONFIG_SYS_HID0_INIT            0x000000000
 233 #define CONFIG_SYS_HID0_FINAL           (HID0_ENABLE_MACHINE_CHECK | \
 234                                          HID0_ENABLE_INSTRUCTION_CACHE)
 235 #define CONFIG_SYS_HID2                 HID2_HBE
 236
 237 /*
 238  * MMU Setup
 239  */
 240
 241 /* DDR: cache cacheable */
 242 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
 243                                 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 244 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
 245                                         BATU_VS | BATU_VP)
 246 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 247 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 248
 249 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
 250 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR | BATL_PP_RW | \
 251                                 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 252 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \
 253                                         | BATU_VP)
 254 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 255 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 256
 257 /* PRIO1, PIGGY:  icache cacheable, but dcache-inhibit and guarded */
 258 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
 259                                 BATL_MEMCOHERENCE)
 260 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \
 261                                 BATU_VS | BATU_VP)
 262 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
 263                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 264 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 265
 266 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 267 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
 268                                         BATL_MEMCOHERENCE)
 269 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \
 270                                         BATU_VS | BATU_VP)
 271 #define CONFIG_SYS_DBAT3L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
 272                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 273 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 274
 275 /* Stack in dcache: cacheable, no memory coherence */
 276 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 277 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
 278                                         BATU_VS | BATU_VP)
 279 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 280 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 281
 282 /*
 283  * Internal Definitions
 284  */
 285 #define BOOTFLASH_START 0xF0000000
 286
 287 #define CONFIG_KM_CONSOLE_TTY   "ttyS0"
 288
 289 /*
 290  * Environment Configuration
 291  */
 292 #define CONFIG_ENV_OVERWRITE
 293 #ifndef CONFIG_KM_DEF_ENV               /* if not set by keymile-common.h */
 294 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
 295 #endif
 296
 297 #ifndef CONFIG_KM_DEF_ARCH
 298 #define CONFIG_KM_DEF_ARCH      "arch=ppc_82xx\0"
 299 #endif
 300
 301 #define CONFIG_EXTRA_ENV_SETTINGS \
 302         CONFIG_KM_DEF_ENV                                               \
 303         CONFIG_KM_DEF_ARCH                                              \
 304         "newenv="                                                       \
 305                 "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && "  \
 306                 "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0"         \
 307         "unlock=yes\0"                                                  \
 308         ""
 309
 310 #if defined(CONFIG_UEC_ETH)
 311 #define CONFIG_HAS_ETH0
 312 #endif
 313
 314 /*
 315  * System IO Setup
 316  */
 317 #define CONFIG_SYS_SICRH                (SICRH_UC1EOBI | SICRH_UC2E1OBI)
 318
 319 /**
 320  * DDR RAM settings
 321  */
 322 #define CONFIG_SYS_DDR_SDRAM_CFG (\
 323         SDRAM_CFG_SDRAM_TYPE_DDR2 | \
 324         SDRAM_CFG_SREN | \
 325         SDRAM_CFG_HSE)
 326
 327 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
 328
 329 /**
 330  * KMCOGE5NE has 512 MB RAM
 331  */
 332 #define CONFIG_SYS_DDR_CS0_CONFIG (\
 333         CSCONFIG_EN | \
 334         CSCONFIG_AP | \
 335         CSCONFIG_ODT_WR_ONLY_CURRENT | \
 336         CSCONFIG_BANK_BIT_3 | \
 337         CSCONFIG_ROW_BIT_13 | \
 338         CSCONFIG_COL_BIT_10)
 339
 340 #define CONFIG_SYS_DDR_CLK_CNTL (\
 341         DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 342
 343 #define CONFIG_SYS_DDR_INTERVAL (\
 344         (0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
 345         (0x203 << SDRAM_INTERVAL_REFINT_SHIFT))
 346
 347 #define CONFIG_SYS_DDR_CS0_BNDS                 0x0000007f
 348
 349 #define CONFIG_SYS_DDRCDR (\
 350         DDRCDR_EN | \
 351         DDRCDR_Q_DRN)
 352 #define CONFIG_SYS_DDR_MODE             0x47860452
 353 #define CONFIG_SYS_DDR_MODE2            0x8080c000
 354
 355 #define CONFIG_SYS_DDR_TIMING_0 (\
 356         (2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
 357         (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
 358         (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
 359         (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
 360         (0 << TIMING_CFG0_WWT_SHIFT) | \
 361         (0 << TIMING_CFG0_RRT_SHIFT) | \
 362         (0 << TIMING_CFG0_WRT_SHIFT) | \
 363         (0 << TIMING_CFG0_RWT_SHIFT))
 364
 365 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \
 366                                  (2 << TIMING_CFG1_WRTORD_SHIFT) | \
 367                                  (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
 368                                  (3 << TIMING_CFG1_WRREC_SHIFT) | \
 369                                  (7 << TIMING_CFG1_REFREC_SHIFT) | \
 370                                  (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
 371                                  (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
 372                                  (3 << TIMING_CFG1_PRETOACT_SHIFT))
 373
 374 #define CONFIG_SYS_DDR_TIMING_2 (\
 375         (0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \
 376         (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
 377         (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
 378         (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
 379         (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
 380         (5 << TIMING_CFG2_CPO_SHIFT) | \
 381         (0 << TIMING_CFG2_ADD_LAT_SHIFT))
 382
 383 #define CONFIG_SYS_DDR_TIMING_3                 0x00000000
 384
 385 /* EEprom support */
 386 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 387
 388 /*
 389  * Local Bus Configuration & Clock Setup
 390  */
 391 #define CONFIG_SYS_LCRR_DBYP            LCRR_DBYP
 392 #define CONFIG_SYS_LCRR_EADC            LCRR_EADC_2
 393 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_4
 394
 395 /*
 396  * PAXE on the local bus CS3
 397  */
 398 #define CONFIG_SYS_PAXE_BASE            0xA0000000
 399 #define CONFIG_SYS_PAXE_SIZE            256
 400
 401 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_PAXE_BASE
 402
 403 #define CONFIG_SYS_LBLAWAR3_PRELIM      0x8000001C /* 512MB window size */
 404
 405 #define CONFIG_SYS_BR3_PRELIM (\
 406         CONFIG_SYS_PAXE_BASE | \
 407         (1 << BR_PS_SHIFT) | \
 408         BR_V)
 409
 410 #define CONFIG_SYS_OR3_PRELIM (\
 411         MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \
 412         OR_GPCM_CSNT | \
 413         OR_GPCM_ACS_DIV2 | \
 414         OR_GPCM_SCY_2 | \
 415         OR_GPCM_TRLX | \
 416         OR_GPCM_EAD)
 417
 418 /*
 419  * BFTIC3 on the local bus CS4
 420  */
 421 #define CONFIG_SYS_BFTIC3_BASE                  0xB0000000
 422 #define CONFIG_SYS_BFTIC3_SIZE                  256
 423
 424 #define CONFIG_SYS_BR4_PRELIM (\
 425         CONFIG_SYS_BFTIC3_BASE |\
 426         (1 << BR_PS_SHIFT) | \
 427         BR_V)
 428
 429 #define CONFIG_SYS_OR4_PRELIM (\
 430         MEG_TO_AM(CONFIG_SYS_BFTIC3_SIZE) |\
 431         OR_GPCM_CSNT | \
 432         OR_GPCM_ACS_DIV2 |\
 433         OR_GPCM_SCY_2 |\
 434         OR_GPCM_TRLX |\
 435         OR_GPCM_EAD)
 436
 437 /*
 438  * MMU Setup
 439  */
 440
 441 /* PAXE:  icache cacheable, but dcache-inhibit and guarded */
 442 #define CONFIG_SYS_IBAT5L (\
 443         CONFIG_SYS_PAXE_BASE | \
 444         BATL_PP_10 | \
 445         BATL_MEMCOHERENCE)
 446
 447 #define CONFIG_SYS_IBAT5U (\
 448         CONFIG_SYS_PAXE_BASE | \
 449         BATU_BL_256M | \
 450         BATU_VS | \
 451         BATU_VP)
 452
 453 #define CONFIG_SYS_DBAT5L (\
 454         CONFIG_SYS_PAXE_BASE | \
 455         BATL_PP_10 | \
 456         BATL_CACHEINHIBIT | \
 457         BATL_GUARDEDSTORAGE)
 458
 459 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 460
 461 /* BFTIC3:  icache cacheable, but dcache-inhibit and guarded */
 462 #define CONFIG_SYS_IBAT6L (\
 463         CONFIG_SYS_BFTIC3_BASE | \
 464         BATL_PP_10 | \
 465         BATL_MEMCOHERENCE)
 466
 467 #define CONFIG_SYS_IBAT6U (\
 468         CONFIG_SYS_BFTIC3_BASE | \
 469         BATU_BL_256M | \
 470         BATU_VS | \
 471         BATU_VP)
 472
 473 #define CONFIG_SYS_DBAT6L (\
 474         CONFIG_SYS_BFTIC3_BASE | \
 475         BATL_PP_10 | \
 476         BATL_CACHEINHIBIT | \
 477         BATL_GUARDEDSTORAGE)
 478
 479 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 480
 481 /* DDR/LBC SDRAM next 256M: cacheable */
 482 #define CONFIG_SYS_IBAT7L (\
 483         CONFIG_SYS_SDRAM_BASE2 |\
 484         BATL_PP_10 |\
 485         BATL_CACHEINHIBIT |\
 486         BATL_GUARDEDSTORAGE)
 487
 488 #define CONFIG_SYS_IBAT7U (\
 489         CONFIG_SYS_SDRAM_BASE2 |\
 490         BATU_BL_256M |\
 491         BATU_VS |\
 492         BATU_VP)
 493 /* enable POST tests */
 494 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS)
 495 #define CONFIG_POST_EXTERNAL_WORD_FUNCS /* use own functions, not generic */
 496 #define CPM_POST_WORD_ADDR  CONFIG_SYS_MEMTEST_END
 497 #define CONFIG_TESTPIN_REG  gprt3       /* for kmcoge5ne */
 498 #define CONFIG_TESTPIN_MASK 0x20        /* for kmcoge5ne */
 499
 500 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 501 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 502
 503 #endif /* CONFIG */