1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Holger Brunck, Keymile GmbH Hannover, <holger.brunck@keymile.com>
5 * Christian Herzig, Keymile AG Switzerland, <christian.herzig@keymile.com>
11 /* KMBEC FPGA (PRIO) */
12 #define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
13 #define CONFIG_SYS_KMBEC_FPGA_SIZE 64
15 #define CONFIG_HOSTNAME "kmcoge5ne"
16 #define CONFIG_KM_BOARD_NAME "kmcoge5ne"
17 #define CONFIG_KM_DEF_NETDEV "netdev=eth1\0"
18 #define CONFIG_NAND_ECC_BCH
19 #define CONFIG_NAND_KMETER1
20 #define CONFIG_SYS_MAX_NAND_DEVICE 1
21 #define NAND_MAX_CHIPS 1
22 #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
24 #define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0"
25 #define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1"
28 * High Level Configuration Options
30 #define CONFIG_QE /* Has QE */
32 /* include common defines/options for all Keymile boards */
33 #include "km/keymile-common.h"
34 #include "km/km-powerpc.h"
39 #define CONFIG_83XX_CLKIN 66000000
40 #define CONFIG_SYS_CLK_FREQ 66000000
41 #define CONFIG_83XX_PCICLK 66000000
46 #define CONFIG_SYS_IMMR 0xE0000000
49 * Bus Arbitration Configuration Register (ACR)
51 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */
52 #define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */
53 #define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */
54 #define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */
59 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
60 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
61 #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
63 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
64 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
65 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
67 #define CFG_83XX_DDR_USES_CS0
70 * Manually set up DDR parameters
73 #define CONFIG_SYS_DDR_SIZE 2048 /* MB */
78 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
79 #define CONFIG_SYS_FLASH_BASE 0xF0000000
81 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
82 #define CONFIG_SYS_RAMBOOT
85 /* Reserve 768 kB for Mon */
86 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
89 * Initial RAM Base Address Setup
91 #define CONFIG_SYS_INIT_RAM_LOCK
92 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
93 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */
94 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
95 GENERATED_GBL_DATA_SIZE)
98 * Init Local Bus Memory Controller:
100 * Bank Bus Machine PortSz Size Device
101 * ---- --- ------- ------ ----- ------
102 * 0 Local GPCM 16 bit 256MB FLASH
103 * 1 Local GPCM 8 bit 128MB GPIO/PIGGY
107 * FLASH on the Local Bus
109 #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
111 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
112 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
114 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
115 BR_PS_16 | /* 16 bit port size */ \
116 BR_MS_GPCM | /* MSEL = GPCM */ \
119 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
120 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
122 OR_GPCM_TRLX_SET | OR_GPCM_EAD)
124 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
125 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
126 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
129 * PRIO1/PIGGY on the local bus CS1
131 /* Window base at flash base */
132 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE
133 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB)
135 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \
136 BR_PS_8 | /* 8 bit port size */ \
137 BR_MS_GPCM | /* MSEL = GPCM */ \
139 #define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \
140 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
142 OR_GPCM_TRLX_SET | OR_GPCM_EAD)
147 #define CONFIG_SYS_NS16550_SERIAL
148 #define CONFIG_SYS_NS16550_REG_SIZE 1
149 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
151 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
152 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
155 * QE UEC ethernet configuration
157 #define CONFIG_UEC_ETH
158 #define CONFIG_ETHPRIME "UEC0"
160 #define CONFIG_UEC_ETH1 /* GETH1 */
161 #define UEC_VERBOSE_DEBUG 1
163 #ifdef CONFIG_UEC_ETH1
164 #define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */
165 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
166 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK17
167 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
168 #define CONFIG_SYS_UEC1_PHY_ADDR 0
169 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
170 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
177 #ifndef CONFIG_SYS_RAMBOOT
178 #ifndef CONFIG_ENV_ADDR
179 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
180 CONFIG_SYS_MONITOR_LEN)
182 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
183 #ifndef CONFIG_ENV_OFFSET
184 #define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN)
187 /* Address and size of Redundant Environment Sector */
188 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
189 CONFIG_ENV_SECT_SIZE)
190 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
192 #else /* CFG_SYS_RAMBOOT */
193 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
194 #define CONFIG_ENV_SIZE 0x2000
195 #endif /* CFG_SYS_RAMBOOT */
198 #define CONFIG_SYS_I2C
199 #define CONFIG_SYS_NUM_I2C_BUSES 4
200 #define CONFIG_SYS_I2C_MAX_HOPS 1
201 #define CONFIG_SYS_I2C_FSL
202 #define CONFIG_SYS_FSL_I2C_SPEED 200000
203 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
204 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
205 #define CONFIG_SYS_I2C_OFFSET 0x3000
206 #define CONFIG_SYS_FSL_I2C2_SPEED 200000
207 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
208 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
209 #define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \
210 {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
211 {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
212 {1, {I2C_NULL_HOP} } }
214 #define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/
216 #if defined(CONFIG_CMD_NAND)
217 #define CONFIG_NAND_KMETER1
218 #define CONFIG_SYS_MAX_NAND_DEVICE 1
219 #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE
223 * For booting Linux, the board info and command line data
224 * have to be in the first 8 MB of memory, since this is
225 * the maximum mapped by the Linux kernel during initialization.
227 #define CONFIG_SYS_BOOTMAPSZ (8 << 20)
232 #define CONFIG_SYS_HID0_INIT 0x000000000
233 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
234 HID0_ENABLE_INSTRUCTION_CACHE)
235 #define CONFIG_SYS_HID2 HID2_HBE
241 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
243 /* DDR: cache cacheable */
244 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
245 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
246 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
248 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
249 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
251 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
252 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
253 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
254 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \
256 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
257 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
259 /* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */
260 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
262 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \
264 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
265 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
266 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
268 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
269 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
271 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \
273 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
274 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
275 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
277 /* Stack in dcache: cacheable, no memory coherence */
278 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
279 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
281 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
282 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
285 * Internal Definitions
287 #define BOOTFLASH_START 0xF0000000
289 #define CONFIG_KM_CONSOLE_TTY "ttyS0"
292 * Environment Configuration
294 #define CONFIG_ENV_OVERWRITE
295 #ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
296 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
299 #ifndef CONFIG_KM_DEF_ARCH
300 #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
303 #define CONFIG_EXTRA_ENV_SETTINGS \
307 "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \
308 "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \
312 #if defined(CONFIG_UEC_ETH)
313 #define CONFIG_HAS_ETH0
319 #define CONFIG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI)
322 * Hardware Reset Configuration Word
324 #define CONFIG_SYS_HRCW_LOW (\
325 HRCWL_CSB_TO_CLKIN_4X1 | \
326 HRCWL_CORE_TO_CSB_2X1 | \
327 HRCWL_CE_PLL_VCO_DIV_2 | \
330 #define CONFIG_SYS_HRCW_HIGH (\
331 HRCWH_CORE_ENABLE | \
332 HRCWH_FROM_0X00000100 | \
333 HRCWH_BOOTSEQ_DISABLE | \
334 HRCWH_SW_WATCHDOG_DISABLE | \
335 HRCWH_ROM_LOC_LOCAL_16BIT | \
343 #define CONFIG_SYS_DDR_SDRAM_CFG (\
344 SDRAM_CFG_SDRAM_TYPE_DDR2 | \
348 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
351 * KMCOGE5NE has 512 MB RAM
353 #define CONFIG_SYS_DDR_CS0_CONFIG (\
356 CSCONFIG_ODT_WR_ONLY_CURRENT | \
357 CSCONFIG_BANK_BIT_3 | \
358 CSCONFIG_ROW_BIT_13 | \
361 #define CONFIG_SYS_DDR_CLK_CNTL (\
362 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
364 #define CONFIG_SYS_DDR_INTERVAL (\
365 (0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
366 (0x203 << SDRAM_INTERVAL_REFINT_SHIFT))
368 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
370 #define CONFIG_SYS_DDRCDR (\
373 #define CONFIG_SYS_DDR_MODE 0x47860452
374 #define CONFIG_SYS_DDR_MODE2 0x8080c000
376 #define CONFIG_SYS_DDR_TIMING_0 (\
377 (2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
378 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
379 (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
380 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
381 (0 << TIMING_CFG0_WWT_SHIFT) | \
382 (0 << TIMING_CFG0_RRT_SHIFT) | \
383 (0 << TIMING_CFG0_WRT_SHIFT) | \
384 (0 << TIMING_CFG0_RWT_SHIFT))
386 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \
387 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
388 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
389 (3 << TIMING_CFG1_WRREC_SHIFT) | \
390 (7 << TIMING_CFG1_REFREC_SHIFT) | \
391 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
392 (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
393 (3 << TIMING_CFG1_PRETOACT_SHIFT))
395 #define CONFIG_SYS_DDR_TIMING_2 (\
396 (0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \
397 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
398 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
399 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
400 (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
401 (5 << TIMING_CFG2_CPO_SHIFT) | \
402 (0 << TIMING_CFG2_ADD_LAT_SHIFT))
404 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
407 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
410 * Local Bus Configuration & Clock Setup
412 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
413 #define CONFIG_SYS_LCRR_EADC LCRR_EADC_2
414 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
417 * PAXE on the local bus CS3
419 #define CONFIG_SYS_PAXE_BASE 0xA0000000
420 #define CONFIG_SYS_PAXE_SIZE 256
422 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PAXE_BASE
424 #define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000001C /* 512MB window size */
426 #define CONFIG_SYS_BR3_PRELIM (\
427 CONFIG_SYS_PAXE_BASE | \
428 (1 << BR_PS_SHIFT) | \
431 #define CONFIG_SYS_OR3_PRELIM (\
432 MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \
440 * BFTIC3 on the local bus CS4
442 #define CONFIG_SYS_BFTIC3_BASE 0xB0000000
443 #define CONFIG_SYS_BFTIC3_SIZE 256
445 #define CONFIG_SYS_BR4_PRELIM (\
446 CONFIG_SYS_BFTIC3_BASE |\
447 (1 << BR_PS_SHIFT) | \
450 #define CONFIG_SYS_OR4_PRELIM (\
451 MEG_TO_AM(CONFIG_SYS_BFTIC3_SIZE) |\
462 /* PAXE: icache cacheable, but dcache-inhibit and guarded */
463 #define CONFIG_SYS_IBAT5L (\
464 CONFIG_SYS_PAXE_BASE | \
468 #define CONFIG_SYS_IBAT5U (\
469 CONFIG_SYS_PAXE_BASE | \
474 #define CONFIG_SYS_DBAT5L (\
475 CONFIG_SYS_PAXE_BASE | \
477 BATL_CACHEINHIBIT | \
480 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
482 /* BFTIC3: icache cacheable, but dcache-inhibit and guarded */
483 #define CONFIG_SYS_IBAT6L (\
484 CONFIG_SYS_BFTIC3_BASE | \
488 #define CONFIG_SYS_IBAT6U (\
489 CONFIG_SYS_BFTIC3_BASE | \
494 #define CONFIG_SYS_DBAT6L (\
495 CONFIG_SYS_BFTIC3_BASE | \
497 BATL_CACHEINHIBIT | \
500 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
502 /* DDR/LBC SDRAM next 256M: cacheable */
503 #define CONFIG_SYS_IBAT7L (\
504 CONFIG_SYS_SDRAM_BASE2 |\
509 #define CONFIG_SYS_IBAT7U (\
510 CONFIG_SYS_SDRAM_BASE2 |\
514 /* enable POST tests */
515 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS)
516 #define CONFIG_POST_EXTERNAL_WORD_FUNCS /* use own functions, not generic */
517 #define CPM_POST_WORD_ADDR CONFIG_SYS_MEMTEST_END
518 #define CONFIG_TESTPIN_REG gprt3 /* for kmcoge5ne */
519 #define CONFIG_TESTPIN_MASK 0x20 /* for kmcoge5ne */
521 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
522 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U