1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Holger Brunck, Keymile GmbH Hannover, <holger.brunck@keymile.com>
5 * Christian Herzig, Keymile AG Switzerland, <christian.herzig@keymile.com>
11 /* KMBEC FPGA (PRIO) */
12 #define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
13 #define CONFIG_SYS_KMBEC_FPGA_SIZE 64
15 #if defined CONFIG_KMETER1
16 #define CONFIG_HOSTNAME "kmeter1"
17 #define CONFIG_KM_BOARD_NAME "kmeter1"
18 #define CONFIG_KM_DEF_NETDEV "netdev=eth2\0"
19 #elif defined CONFIG_KMCOGE5NE
20 #define CONFIG_HOSTNAME "kmcoge5ne"
21 #define CONFIG_KM_BOARD_NAME "kmcoge5ne"
22 #define CONFIG_KM_DEF_NETDEV "netdev=eth1\0"
23 #define CONFIG_NAND_ECC_BCH
24 #define CONFIG_NAND_KMETER1
25 #define CONFIG_SYS_MAX_NAND_DEVICE 1
26 #define NAND_MAX_CHIPS 1
27 #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
29 #define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0"
30 #define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1"
32 #error ("Board not supported")
36 * High Level Configuration Options
38 #define CONFIG_QE /* Has QE */
40 /* include common defines/options for all 83xx Keymile boards */
41 #include "km/km83xx-common.h"
46 #define CONFIG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI)
49 * Hardware Reset Configuration Word
51 #define CONFIG_SYS_HRCW_LOW (\
52 HRCWL_CSB_TO_CLKIN_4X1 | \
53 HRCWL_CORE_TO_CSB_2X1 | \
54 HRCWL_CE_PLL_VCO_DIV_2 | \
57 #define CONFIG_SYS_HRCW_HIGH (\
59 HRCWH_FROM_0X00000100 | \
60 HRCWH_BOOTSEQ_DISABLE | \
61 HRCWH_SW_WATCHDOG_DISABLE | \
62 HRCWH_ROM_LOC_LOCAL_16BIT | \
70 #define CONFIG_SYS_DDR_SDRAM_CFG (\
71 SDRAM_CFG_SDRAM_TYPE_DDR2 | \
75 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
77 #ifdef CONFIG_KMCOGE5NE
79 * KMCOGE5NE has 512 MB RAM
81 #define CONFIG_SYS_DDR_CS0_CONFIG (\
84 CSCONFIG_ODT_WR_ONLY_CURRENT | \
85 CSCONFIG_BANK_BIT_3 | \
86 CSCONFIG_ROW_BIT_13 | \
89 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
90 CSCONFIG_ROW_BIT_13 | \
91 CSCONFIG_COL_BIT_10 | \
92 CSCONFIG_ODT_WR_ONLY_CURRENT)
95 #define CONFIG_SYS_DDR_CLK_CNTL (\
96 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
98 #define CONFIG_SYS_DDR_INTERVAL (\
99 (0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
100 (0x203 << SDRAM_INTERVAL_REFINT_SHIFT))
102 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
104 #define CONFIG_SYS_DDRCDR (\
107 #define CONFIG_SYS_DDR_MODE 0x47860452
108 #define CONFIG_SYS_DDR_MODE2 0x8080c000
110 #define CONFIG_SYS_DDR_TIMING_0 (\
111 (2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
112 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
113 (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
114 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
115 (0 << TIMING_CFG0_WWT_SHIFT) | \
116 (0 << TIMING_CFG0_RRT_SHIFT) | \
117 (0 << TIMING_CFG0_WRT_SHIFT) | \
118 (0 << TIMING_CFG0_RWT_SHIFT))
120 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \
121 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
122 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
123 (3 << TIMING_CFG1_WRREC_SHIFT) | \
124 (7 << TIMING_CFG1_REFREC_SHIFT) | \
125 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
126 (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
127 (3 << TIMING_CFG1_PRETOACT_SHIFT))
129 #define CONFIG_SYS_DDR_TIMING_2 (\
130 (0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \
131 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
132 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
133 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
134 (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
135 (5 << TIMING_CFG2_CPO_SHIFT) | \
136 (0 << TIMING_CFG2_ADD_LAT_SHIFT))
138 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
141 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
144 * Local Bus Configuration & Clock Setup
146 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
147 #define CONFIG_SYS_LCRR_EADC LCRR_EADC_2
148 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
151 * PAXE on the local bus CS3
153 #define CONFIG_SYS_PAXE_BASE 0xA0000000
154 #define CONFIG_SYS_PAXE_SIZE 256
156 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PAXE_BASE
158 #define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000001C /* 512MB window size */
160 #define CONFIG_SYS_BR3_PRELIM (\
161 CONFIG_SYS_PAXE_BASE | \
162 (1 << BR_PS_SHIFT) | \
165 #define CONFIG_SYS_OR3_PRELIM (\
166 MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \
173 #ifdef CONFIG_KMCOGE5NE
175 * BFTIC3 on the local bus CS4
177 #define CONFIG_SYS_BFTIC3_BASE 0xB0000000
178 #define CONFIG_SYS_BFTIC3_SIZE 256
180 #define CONFIG_SYS_BR4_PRELIM (\
181 CONFIG_SYS_BFTIC3_BASE |\
182 (1 << BR_PS_SHIFT) | \
185 #define CONFIG_SYS_OR4_PRELIM (\
186 MEG_TO_AM(CONFIG_SYS_BFTIC3_SIZE) |\
198 /* PAXE: icache cacheable, but dcache-inhibit and guarded */
199 #define CONFIG_SYS_IBAT5L (\
200 CONFIG_SYS_PAXE_BASE | \
204 #define CONFIG_SYS_IBAT5U (\
205 CONFIG_SYS_PAXE_BASE | \
210 #define CONFIG_SYS_DBAT5L (\
211 CONFIG_SYS_PAXE_BASE | \
213 BATL_CACHEINHIBIT | \
216 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
218 #ifdef CONFIG_KMCOGE5NE
219 /* BFTIC3: icache cacheable, but dcache-inhibit and guarded */
220 #define CONFIG_SYS_IBAT6L (\
221 CONFIG_SYS_BFTIC3_BASE | \
225 #define CONFIG_SYS_IBAT6U (\
226 CONFIG_SYS_BFTIC3_BASE | \
231 #define CONFIG_SYS_DBAT6L (\
232 CONFIG_SYS_BFTIC3_BASE | \
234 BATL_CACHEINHIBIT | \
237 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
239 /* DDR/LBC SDRAM next 256M: cacheable */
240 #define CONFIG_SYS_IBAT7L (\
241 CONFIG_SYS_SDRAM_BASE2 |\
246 #define CONFIG_SYS_IBAT7U (\
247 CONFIG_SYS_SDRAM_BASE2 |\
251 /* enable POST tests */
252 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS)
253 #define CONFIG_POST_EXTERNAL_WORD_FUNCS /* use own functions, not generic */
254 #define CPM_POST_WORD_ADDR CONFIG_SYS_MEMTEST_END
255 #define CONFIG_TESTPIN_REG gprt3 /* for kmcoge5ne */
256 #define CONFIG_TESTPIN_MASK 0x20 /* for kmcoge5ne */
259 #define CONFIG_SYS_IBAT6L (0)
260 #define CONFIG_SYS_IBAT6U (0)
261 #define CONFIG_SYS_IBAT7L (0)
262 #define CONFIG_SYS_IBAT7U (0)
263 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
264 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
267 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
268 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U