include/configs/km8360.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2012
   4  * Holger Brunck, Keymile GmbH Hannover, <holger.brunck@keymile.com>
   5  * Christian Herzig, Keymile AG Switzerland, <christian.herzig@keymile.com>
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 /* KMBEC FPGA (PRIO) */
  12 #define CONFIG_SYS_KMBEC_FPGA_BASE      0xE8000000
  13 #define CONFIG_SYS_KMBEC_FPGA_SIZE      64
  14
  15 #if defined CONFIG_KMETER1
  16 #define CONFIG_HOSTNAME         "kmeter1"
  17 #define CONFIG_KM_BOARD_NAME   "kmeter1"
  18 #define CONFIG_KM_DEF_NETDEV    "netdev=eth2\0"
  19 #elif defined CONFIG_KMCOGE5NE
  20 #define CONFIG_HOSTNAME         "kmcoge5ne"
  21 #define CONFIG_KM_BOARD_NAME    "kmcoge5ne"
  22 #define CONFIG_KM_DEF_NETDEV    "netdev=eth1\0"
  23 #define CONFIG_NAND_ECC_BCH
  24 #define CONFIG_NAND_KMETER1
  25 #define CONFIG_SYS_MAX_NAND_DEVICE              1
  26 #define NAND_MAX_CHIPS                          1
  27 #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
  28
  29 #define CONFIG_KM_UBI_PARTITION_NAME_BOOT       "ubi0"
  30 #define CONFIG_KM_UBI_PARTITION_NAME_APP        "ubi1"
  31 #else
  32 #error ("Board not supported")
  33 #endif
  34
  35 /*
  36  * High Level Configuration Options
  37  */
  38 #define CONFIG_QE                       /* Has QE */
  39
  40 /* include common defines/options for all Keymile boards */
  41 #include "km/keymile-common.h"
  42 #include "km/km-powerpc.h"
  43
  44 /*
  45  * System Clock Setup
  46  */
  47 #define CONFIG_83XX_CLKIN               66000000
  48 #define CONFIG_SYS_CLK_FREQ             66000000
  49 #define CONFIG_83XX_PCICLK              66000000
  50
  51 /*
  52  * IMMR new address
  53  */
  54 #define CONFIG_SYS_IMMR         0xE0000000
  55
  56 /*
  57  * Bus Arbitration Configuration Register (ACR)
  58  */
  59 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* pipeline depth 4 transactions */
  60 #define CONFIG_SYS_ACR_RPTCNT   3       /* 4 consecutive transactions */
  61 #define CONFIG_SYS_ACR_APARK    0       /* park bus to master (below) */
  62 #define CONFIG_SYS_ACR_PARKM    3       /* parking master = QuiccEngine */
  63
  64 /*
  65  * DDR Setup
  66  */
  67 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
  68 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  69 #define CONFIG_SYS_SDRAM_BASE2  (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
  70
  71 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  72 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN | \
  73                                         DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  74
  75 #define CFG_83XX_DDR_USES_CS0
  76
  77 /*
  78  * Manually set up DDR parameters
  79  */
  80 #define CONFIG_DDR_II
  81 #define CONFIG_SYS_DDR_SIZE             2048 /* MB */
  82
  83 /*
  84  * The reserved memory
  85  */
  86 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  87 #define CONFIG_SYS_FLASH_BASE           0xF0000000
  88
  89 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  90 #define CONFIG_SYS_RAMBOOT
  91 #endif
  92
  93 /* Reserve 768 kB for Mon */
  94 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
  95
  96 /*
  97  * Initial RAM Base Address Setup
  98  */
  99 #define CONFIG_SYS_INIT_RAM_LOCK
 100 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 101 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* End of used area in RAM */
 102 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 103                                                 GENERATED_GBL_DATA_SIZE)
 104
 105 /*
 106  * Init Local Bus Memory Controller:
 107  *
 108  * Bank Bus     Machine PortSz  Size  Device
 109  * ---- ---     ------- ------  -----  ------
 110  *  0   Local   GPCM    16 bit  256MB FLASH
 111  *  1   Local   GPCM     8 bit  128MB GPIO/PIGGY
 112  *
 113  */
 114 /*
 115  * FLASH on the Local Bus
 116  */
 117 #define CONFIG_SYS_FLASH_SIZE           256 /* max FLASH size is 256M */
 118
 119 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 120 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_256MB)
 121
 122 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE | \
 123                                 BR_PS_16 | /* 16 bit port size */ \
 124                                 BR_MS_GPCM | /* MSEL = GPCM */ \
 125                                 BR_V)
 126
 127 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
 128                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 129                                 OR_GPCM_SCY_5 | \
 130                                 OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 131
 132 #define CONFIG_SYS_MAX_FLASH_BANKS      1   /* max num of flash banks   */
 133 #define CONFIG_SYS_MAX_FLASH_SECT       512 /* max num of sects on one chip */
 134 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
 135
 136 /*
 137  * PRIO1/PIGGY on the local bus CS1
 138  */
 139 /* Window base at flash base */
 140 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_KMBEC_FPGA_BASE
 141 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_128MB)
 142
 143 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_KMBEC_FPGA_BASE | \
 144                                 BR_PS_8 | /* 8 bit port size */ \
 145                                 BR_MS_GPCM | /* MSEL = GPCM */ \
 146                                 BR_V)
 147 #define CONFIG_SYS_OR1_PRELIM   (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \
 148                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 149                                 OR_GPCM_SCY_2 | \
 150                                 OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 151
 152 /*
 153  * Serial Port
 154  */
 155 #define CONFIG_SYS_NS16550_SERIAL
 156 #define CONFIG_SYS_NS16550_REG_SIZE     1
 157 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 158
 159 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 160 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 161
 162 /*
 163  * QE UEC ethernet configuration
 164  */
 165 #define CONFIG_UEC_ETH
 166 #define CONFIG_ETHPRIME         "UEC0"
 167
 168 #if !defined(CONFIG_ARCH_MPC8309)
 169 #define CONFIG_UEC_ETH1         /* GETH1 */
 170 #define UEC_VERBOSE_DEBUG       1
 171 #endif
 172
 173 #ifdef CONFIG_UEC_ETH1
 174 #define CONFIG_SYS_UEC1_UCC_NUM 3       /* UCC4 */
 175 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK_NONE /* not used in RMII Mode */
 176 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK17
 177 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 178 #define CONFIG_SYS_UEC1_PHY_ADDR        0
 179 #define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_RMII
 180 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 181 #endif
 182
 183 /*
 184  * Environment
 185  */
 186
 187 #ifndef CONFIG_SYS_RAMBOOT
 188 #ifndef CONFIG_ENV_ADDR
 189 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 190                                         CONFIG_SYS_MONITOR_LEN)
 191 #endif
 192 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 193 #ifndef CONFIG_ENV_OFFSET
 194 #define CONFIG_ENV_OFFSET       (CONFIG_SYS_MONITOR_LEN)
 195 #endif
 196
 197 /* Address and size of Redundant Environment Sector     */
 198 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + \
 199                                                 CONFIG_ENV_SECT_SIZE)
 200 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 201
 202 #else /* CFG_SYS_RAMBOOT */
 203 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 204 #define CONFIG_ENV_SIZE         0x2000
 205 #endif /* CFG_SYS_RAMBOOT */
 206
 207 /* I2C */
 208 #define CONFIG_SYS_I2C
 209 #define CONFIG_SYS_NUM_I2C_BUSES        4
 210 #define CONFIG_SYS_I2C_MAX_HOPS         1
 211 #define CONFIG_SYS_I2C_FSL
 212 #define CONFIG_SYS_FSL_I2C_SPEED        200000
 213 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 214 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 215 #define CONFIG_SYS_I2C_OFFSET           0x3000
 216 #define CONFIG_SYS_FSL_I2C2_SPEED       200000
 217 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 218 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 219 #define CONFIG_SYS_I2C_BUSES    {{0, {I2C_NULL_HOP} }, \
 220                 {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
 221                 {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
 222                 {1, {I2C_NULL_HOP} } }
 223
 224 #define CONFIG_KM_IVM_BUS               2       /* I2C2 (Mux-Port 1)*/
 225
 226 #if defined(CONFIG_CMD_NAND)
 227 #define CONFIG_NAND_KMETER1
 228 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 229 #define CONFIG_SYS_NAND_BASE            CONFIG_SYS_KMBEC_FPGA_BASE
 230 #endif
 231
 232 /*
 233  * For booting Linux, the board info and command line data
 234  * have to be in the first 8 MB of memory, since this is
 235  * the maximum mapped by the Linux kernel during initialization.
 236  */
 237 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)
 238
 239 /*
 240  * Core HID Setup
 241  */
 242 #define CONFIG_SYS_HID0_INIT            0x000000000
 243 #define CONFIG_SYS_HID0_FINAL           (HID0_ENABLE_MACHINE_CHECK | \
 244                                          HID0_ENABLE_INSTRUCTION_CACHE)
 245 #define CONFIG_SYS_HID2                 HID2_HBE
 246
 247 /*
 248  * MMU Setup
 249  */
 250
 251 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 252
 253 /* DDR: cache cacheable */
 254 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
 255                                 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 256 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
 257                                         BATU_VS | BATU_VP)
 258 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 259 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 260
 261 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
 262 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR | BATL_PP_RW | \
 263                                 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 264 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \
 265                                         | BATU_VP)
 266 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 267 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 268
 269 /* PRIO1, PIGGY:  icache cacheable, but dcache-inhibit and guarded */
 270 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
 271                                 BATL_MEMCOHERENCE)
 272 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \
 273                                 BATU_VS | BATU_VP)
 274 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
 275                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 276 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 277
 278 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 279 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
 280                                         BATL_MEMCOHERENCE)
 281 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \
 282                                         BATU_VS | BATU_VP)
 283 #define CONFIG_SYS_DBAT3L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
 284                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 285 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 286
 287 /* Stack in dcache: cacheable, no memory coherence */
 288 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 289 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
 290                                         BATU_VS | BATU_VP)
 291 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 292 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 293
 294 /*
 295  * Internal Definitions
 296  */
 297 #define BOOTFLASH_START 0xF0000000
 298
 299 #define CONFIG_KM_CONSOLE_TTY   "ttyS0"
 300
 301 /*
 302  * Environment Configuration
 303  */
 304 #define CONFIG_ENV_OVERWRITE
 305 #ifndef CONFIG_KM_DEF_ENV               /* if not set by keymile-common.h */
 306 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
 307 #endif
 308
 309 #ifndef CONFIG_KM_DEF_ARCH
 310 #define CONFIG_KM_DEF_ARCH      "arch=ppc_82xx\0"
 311 #endif
 312
 313 #define CONFIG_EXTRA_ENV_SETTINGS \
 314         CONFIG_KM_DEF_ENV                                               \
 315         CONFIG_KM_DEF_ARCH                                              \
 316         "newenv="                                                       \
 317                 "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && "  \
 318                 "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0"         \
 319         "unlock=yes\0"                                                  \
 320         ""
 321
 322 #if defined(CONFIG_UEC_ETH)
 323 #define CONFIG_HAS_ETH0
 324 #endif
 325
 326 /*
 327  * System IO Setup
 328  */
 329 #define CONFIG_SYS_SICRH                (SICRH_UC1EOBI | SICRH_UC2E1OBI)
 330
 331 /*
 332  * Hardware Reset Configuration Word
 333  */
 334 #define CONFIG_SYS_HRCW_LOW (\
 335         HRCWL_CSB_TO_CLKIN_4X1 | \
 336         HRCWL_CORE_TO_CSB_2X1 | \
 337         HRCWL_CE_PLL_VCO_DIV_2 | \
 338         HRCWL_CE_TO_PLL_1X6)
 339
 340 #define CONFIG_SYS_HRCW_HIGH (\
 341         HRCWH_CORE_ENABLE | \
 342         HRCWH_FROM_0X00000100 | \
 343         HRCWH_BOOTSEQ_DISABLE | \
 344         HRCWH_SW_WATCHDOG_DISABLE | \
 345         HRCWH_ROM_LOC_LOCAL_16BIT | \
 346         HRCWH_BIG_ENDIAN | \
 347         HRCWH_LALE_EARLY | \
 348         HRCWH_LDP_CLEAR)
 349
 350 /**
 351  * DDR RAM settings
 352  */
 353 #define CONFIG_SYS_DDR_SDRAM_CFG (\
 354         SDRAM_CFG_SDRAM_TYPE_DDR2 | \
 355         SDRAM_CFG_SREN | \
 356         SDRAM_CFG_HSE)
 357
 358 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
 359
 360 #ifdef CONFIG_KMCOGE5NE
 361 /**
 362  * KMCOGE5NE has 512 MB RAM
 363  */
 364 #define CONFIG_SYS_DDR_CS0_CONFIG (\
 365         CSCONFIG_EN | \
 366         CSCONFIG_AP | \
 367         CSCONFIG_ODT_WR_ONLY_CURRENT | \
 368         CSCONFIG_BANK_BIT_3 | \
 369         CSCONFIG_ROW_BIT_13 | \
 370         CSCONFIG_COL_BIT_10)
 371 #else
 372 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN | CSCONFIG_AP | \
 373                                          CSCONFIG_ROW_BIT_13 | \
 374                                          CSCONFIG_COL_BIT_10 | \
 375                                          CSCONFIG_ODT_WR_ONLY_CURRENT)
 376 #endif
 377
 378 #define CONFIG_SYS_DDR_CLK_CNTL (\
 379         DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 380
 381 #define CONFIG_SYS_DDR_INTERVAL (\
 382         (0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
 383         (0x203 << SDRAM_INTERVAL_REFINT_SHIFT))
 384
 385 #define CONFIG_SYS_DDR_CS0_BNDS                 0x0000007f
 386
 387 #define CONFIG_SYS_DDRCDR (\
 388         DDRCDR_EN | \
 389         DDRCDR_Q_DRN)
 390 #define CONFIG_SYS_DDR_MODE             0x47860452
 391 #define CONFIG_SYS_DDR_MODE2            0x8080c000
 392
 393 #define CONFIG_SYS_DDR_TIMING_0 (\
 394         (2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
 395         (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
 396         (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
 397         (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
 398         (0 << TIMING_CFG0_WWT_SHIFT) | \
 399         (0 << TIMING_CFG0_RRT_SHIFT) | \
 400         (0 << TIMING_CFG0_WRT_SHIFT) | \
 401         (0 << TIMING_CFG0_RWT_SHIFT))
 402
 403 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \
 404                                  (2 << TIMING_CFG1_WRTORD_SHIFT) | \
 405                                  (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
 406                                  (3 << TIMING_CFG1_WRREC_SHIFT) | \
 407                                  (7 << TIMING_CFG1_REFREC_SHIFT) | \
 408                                  (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
 409                                  (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
 410                                  (3 << TIMING_CFG1_PRETOACT_SHIFT))
 411
 412 #define CONFIG_SYS_DDR_TIMING_2 (\
 413         (0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \
 414         (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
 415         (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
 416         (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
 417         (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
 418         (5 << TIMING_CFG2_CPO_SHIFT) | \
 419         (0 << TIMING_CFG2_ADD_LAT_SHIFT))
 420
 421 #define CONFIG_SYS_DDR_TIMING_3                 0x00000000
 422
 423 /* EEprom support */
 424 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 425
 426 /*
 427  * Local Bus Configuration & Clock Setup
 428  */
 429 #define CONFIG_SYS_LCRR_DBYP            LCRR_DBYP
 430 #define CONFIG_SYS_LCRR_EADC            LCRR_EADC_2
 431 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_4
 432
 433 /*
 434  * PAXE on the local bus CS3
 435  */
 436 #define CONFIG_SYS_PAXE_BASE            0xA0000000
 437 #define CONFIG_SYS_PAXE_SIZE            256
 438
 439 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_PAXE_BASE
 440
 441 #define CONFIG_SYS_LBLAWAR3_PRELIM      0x8000001C /* 512MB window size */
 442
 443 #define CONFIG_SYS_BR3_PRELIM (\
 444         CONFIG_SYS_PAXE_BASE | \
 445         (1 << BR_PS_SHIFT) | \
 446         BR_V)
 447
 448 #define CONFIG_SYS_OR3_PRELIM (\
 449         MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \
 450         OR_GPCM_CSNT | \
 451         OR_GPCM_ACS_DIV2 | \
 452         OR_GPCM_SCY_2 | \
 453         OR_GPCM_TRLX | \
 454         OR_GPCM_EAD)
 455
 456 #ifdef CONFIG_KMCOGE5NE
 457 /*
 458  * BFTIC3 on the local bus CS4
 459  */
 460 #define CONFIG_SYS_BFTIC3_BASE                  0xB0000000
 461 #define CONFIG_SYS_BFTIC3_SIZE                  256
 462
 463 #define CONFIG_SYS_BR4_PRELIM (\
 464         CONFIG_SYS_BFTIC3_BASE |\
 465         (1 << BR_PS_SHIFT) | \
 466         BR_V)
 467
 468 #define CONFIG_SYS_OR4_PRELIM (\
 469         MEG_TO_AM(CONFIG_SYS_BFTIC3_SIZE) |\
 470         OR_GPCM_CSNT | \
 471         OR_GPCM_ACS_DIV2 |\
 472         OR_GPCM_SCY_2 |\
 473         OR_GPCM_TRLX |\
 474         OR_GPCM_EAD)
 475 #endif
 476
 477 /*
 478  * MMU Setup
 479  */
 480
 481 /* PAXE:  icache cacheable, but dcache-inhibit and guarded */
 482 #define CONFIG_SYS_IBAT5L (\
 483         CONFIG_SYS_PAXE_BASE | \
 484         BATL_PP_10 | \
 485         BATL_MEMCOHERENCE)
 486
 487 #define CONFIG_SYS_IBAT5U (\
 488         CONFIG_SYS_PAXE_BASE | \
 489         BATU_BL_256M | \
 490         BATU_VS | \
 491         BATU_VP)
 492
 493 #define CONFIG_SYS_DBAT5L (\
 494         CONFIG_SYS_PAXE_BASE | \
 495         BATL_PP_10 | \
 496         BATL_CACHEINHIBIT | \
 497         BATL_GUARDEDSTORAGE)
 498
 499 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 500
 501 #ifdef CONFIG_KMCOGE5NE
 502 /* BFTIC3:  icache cacheable, but dcache-inhibit and guarded */
 503 #define CONFIG_SYS_IBAT6L (\
 504         CONFIG_SYS_BFTIC3_BASE | \
 505         BATL_PP_10 | \
 506         BATL_MEMCOHERENCE)
 507
 508 #define CONFIG_SYS_IBAT6U (\
 509         CONFIG_SYS_BFTIC3_BASE | \
 510         BATU_BL_256M | \
 511         BATU_VS | \
 512         BATU_VP)
 513
 514 #define CONFIG_SYS_DBAT6L (\
 515         CONFIG_SYS_BFTIC3_BASE | \
 516         BATL_PP_10 | \
 517         BATL_CACHEINHIBIT | \
 518         BATL_GUARDEDSTORAGE)
 519
 520 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 521
 522 /* DDR/LBC SDRAM next 256M: cacheable */
 523 #define CONFIG_SYS_IBAT7L (\
 524         CONFIG_SYS_SDRAM_BASE2 |\
 525         BATL_PP_10 |\
 526         BATL_CACHEINHIBIT |\
 527         BATL_GUARDEDSTORAGE)
 528
 529 #define CONFIG_SYS_IBAT7U (\
 530         CONFIG_SYS_SDRAM_BASE2 |\
 531         BATU_BL_256M |\
 532         BATU_VS |\
 533         BATU_VP)
 534 /* enable POST tests */
 535 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS)
 536 #define CONFIG_POST_EXTERNAL_WORD_FUNCS /* use own functions, not generic */
 537 #define CPM_POST_WORD_ADDR  CONFIG_SYS_MEMTEST_END
 538 #define CONFIG_TESTPIN_REG  gprt3       /* for kmcoge5ne */
 539 #define CONFIG_TESTPIN_MASK 0x20        /* for kmcoge5ne */
 540
 541 #else
 542 #define CONFIG_SYS_IBAT6L       (0)
 543 #define CONFIG_SYS_IBAT6U       (0)
 544 #define CONFIG_SYS_IBAT7L       (0)
 545 #define CONFIG_SYS_IBAT7U       (0)
 546 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 547 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 548 #endif
 549
 550 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 551 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 552
 553 #endif /* CONFIG */