2 * (C) Copyright 2007-2011
3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
12 * High Level Configuration Options
16 #define CONFIG_MPC8247
18 #if defined(CONFIG_MGCOGE)
19 #define CONFIG_HOSTNAME mgcoge
20 #define CONFIG_KM_BOARD_EXTRA_ENV ""
23 #elif defined(CONFIG_MGCOGE3NE)
24 #define CONFIG_HOSTNAME mgcoge3ne
25 #define CONFIG_KM_82XX
26 #define CONFIG_KM_BOARD_EXTRA_ENV "bobcatreset=true\0"
29 #error ("Board unsupported")
32 #define CONFIG_SYS_TEXT_BASE 0xFE000000
34 /* include common defines/options for all Keymile boards */
35 #include "km/keymile-common.h"
36 #include "km/km-powerpc.h"
38 #define CONFIG_SYS_SDRAM_BASE 0x00000000
39 #define CONFIG_SYS_FLASH_BASE 0xFE000000
40 #define CONFIG_SYS_FLASH_SIZE 32
41 #define CONFIG_SYS_FLASH_CFI
42 #define CONFIG_FLASH_CFI_DRIVER
45 #if defined(CONFIG_MGCOGE)
46 #define CONFIG_SYS_MAX_FLASH_BANKS 3
47 /* max num of sects on one chip */
48 #define CONFIG_SYS_MAX_FLASH_SECT 512
50 #define CONFIG_SYS_FLASH_BASE_1 0x50000000
51 #define CONFIG_SYS_FLASH_SIZE_1 32
52 #define CONFIG_SYS_FLASH_BASE_2 0x52000000
53 #define CONFIG_SYS_FLASH_SIZE_2 32
55 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
56 CONFIG_SYS_FLASH_BASE_1, \
57 CONFIG_SYS_FLASH_BASE_2 }
58 #define MTDIDS_DEFAULT "nor3=app"
61 * Bank 1 - 60x bus SDRAM
63 #define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
64 #define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (256 << 20) /* less than 256 MB */
66 /* SDRAM initialization values
69 #define CONFIG_SYS_OR1 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & \
75 #define CONFIG_SYS_PSDMR ( \
76 PSDMR_SDAM_A14_IS_A5 |\
78 PSDMR_SDA10_PBI0_A9 |\
87 #elif defined(CONFIG_MGCOGE3NE)
88 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */
89 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /*
90 * max num of sects on one
94 #define CONFIG_SYS_FLASH_BASE_1 0x50000000
95 #define CONFIG_SYS_FLASH_SIZE_1 128
97 #define CONFIG_SYS_FLASH_SIZE_2 0 /* dummy value to calc SYS_OR5 */
99 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
100 CONFIG_SYS_FLASH_BASE_1 }
102 #define MTDIDS_DEFAULT "nor2=app"
105 * Bank 1 - 60x bus SDRAM
106 * mgcoge3ne has 256MB
107 * mgcoge2ne has 128MB
109 #define SDRAM_MAX_SIZE 0x10000000 /* max. 256 MB */
110 #define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (512 << 20) /* less than 512 MB */
112 #define CONFIG_SYS_OR1 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & \
118 #define CONFIG_SYS_PSDMR ( \
121 PSDMR_BSMA_A13_A15 |\
129 #define CONFIG_SYS_SDRAM_LIST { \
130 { .size = 256 << 20, \
131 .or1 = ORxS_ROWST_PBI1_A4, \
132 .psdmr = PSDMR_SDAM_A17_IS_A5 | PSDMR_SDA10_PBI1_A6, \
134 { .size = 128 << 20, \
135 .or1 = ORxS_ROWST_PBI1_A5, \
136 .psdmr = PSDMR_SDAM_A16_IS_A5 | PSDMR_SDA10_PBI1_A7, \
139 #endif /* defined(CONFIG_MGCOGE3NE) */
141 /* include further common stuff for all keymile 82xx boards */
143 * Select serial console configuration
145 * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
146 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
149 #define CONFIG_CONS_ON_SMC /* Console is on SMC */
150 #undef CONFIG_CONS_ON_SCC /* It's not on SCC */
151 #undef CONFIG_CONS_NONE /* It's not on external UART */
152 #define CONFIG_CONS_INDEX 2 /* SMC2 is used for console */
153 #define CONFIG_SYS_SMC_RXBUFLEN 128
154 #define CONFIG_SYS_MAXIDLE 10
157 * Select ethernet configuration
159 * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
160 * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
163 * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
164 * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
167 #define CONFIG_ETHER_ON_SCC /* Ethernet is on SCC */
168 #undef CONFIG_ETHER_ON_FCC /* Ethernet is not on FCC */
169 #undef CONFIG_ETHER_NONE /* No external Ethernet */
171 #define CONFIG_ETHER_INDEX 4
172 #define CONFIG_HAS_ETH0
173 #define CONFIG_SYS_SCC_TOUT_LOOP 10000000
175 #define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8)
177 #ifndef CONFIG_8260_CLKIN
178 #define CONFIG_8260_CLKIN 66000000 /* in Hz */
181 #define BOOTFLASH_START 0xFE000000
183 #define CONFIG_KM_CONSOLE_TTY "ttyCPM0"
185 #define MTDPARTS_DEFAULT "mtdparts=" \
191 "-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ")"
194 * Default environment settings
196 #define CONFIG_EXTRA_ENV_SETTINGS \
197 CONFIG_KM_BOARD_EXTRA_ENV \
199 "EEprom_ivm=pca9544a:70:4 \0" \
202 "prot off 0xFE0C0000 +0x40000 && " \
203 "era 0xFE0C0000 +0x40000\0" \
207 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
208 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
209 #define CONFIG_SYS_RAMBOOT
212 #define CONFIG_SYS_MONITOR_LEN (768 << 10)
214 #define CONFIG_ENV_IS_IN_FLASH
216 #ifdef CONFIG_ENV_IS_IN_FLASH
217 #define CONFIG_ENV_SECT_SIZE 0x20000
218 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
219 CONFIG_SYS_MONITOR_LEN)
220 #define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN
222 /* Address and size of Redundant Environment Sector */
223 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
224 CONFIG_ENV_SECT_SIZE)
225 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
226 #endif /* CONFIG_ENV_IS_IN_FLASH */
228 /* enable I2C and select the hardware/software driver */
229 #undef CONFIG_HARD_I2C /* I2C with hardware support */
230 #define CONFIG_SOFT_I2C /* I2C bit-banged */
231 #define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed */
232 #define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */
235 * Software (bit-bang) I2C driver configuration
238 #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
239 #define I2C_ACTIVE (iop->pdir |= 0x00010000)
240 #define I2C_TRISTATE (iop->pdir &= ~0x00010000)
241 #define I2C_READ ((iop->pdat & 0x00010000) != 0)
242 #define I2C_SDA(bit) do { \
244 iop->pdat |= 0x00010000; \
246 iop->pdat &= ~0x00010000; \
248 #define I2C_SCL(bit) do { \
250 iop->pdat |= 0x00020000; \
252 iop->pdat &= ~0x00020000; \
254 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
257 void set_sda(int state);
258 void set_scl(int state);
263 /* I2C SYSMON (LM75, AD7414 is almost compatible) */
264 #define CONFIG_DTT_LM75 /* ON Semi's LM75 */
265 #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
266 #define CONFIG_SYS_DTT_MAX_TEMP 70
267 #define CONFIG_SYS_DTT_LOW_TEMP -30
268 #define CONFIG_SYS_DTT_HYSTERESIS 3
269 #define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS)
271 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
273 #define CONFIG_SYS_IMMR 0xF0000000
275 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
276 #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* used size in DPRAM */
277 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
278 GENERATED_GBL_DATA_SIZE)
279 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
281 /* Hard reset configuration word */
282 #define CONFIG_SYS_HRCW_MASTER 0x0604b211
285 #define CONFIG_SYS_HRCW_SLAVE1 0
286 #define CONFIG_SYS_HRCW_SLAVE2 0
287 #define CONFIG_SYS_HRCW_SLAVE3 0
288 #define CONFIG_SYS_HRCW_SLAVE4 0
289 #define CONFIG_SYS_HRCW_SLAVE5 0
290 #define CONFIG_SYS_HRCW_SLAVE6 0
291 #define CONFIG_SYS_HRCW_SLAVE7 0
293 /* Initial Memory map for Linux */
294 #define CONFIG_SYS_BOOTMAPSZ (8 << 20)
296 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
297 #if defined(CONFIG_CMD_KGDB)
298 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
301 #define CONFIG_SYS_HID0_INIT 0
302 #define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE)
304 #define CONFIG_SYS_HID2 0
306 #define CONFIG_SYS_SIUMCR 0x4020c200
307 #define CONFIG_SYS_SYPCR 0xFFFFFF83
308 #define CONFIG_SYS_BCR 0x10000000
309 #define CONFIG_SYS_SCCR (SCCR_PCI_MODE | SCCR_PCI_MODCK)
312 *-----------------------------------------------------------------------
313 * RMR - Reset Mode Register 5-5
314 *-----------------------------------------------------------------------
315 * turn on Checkstop Reset Enable
317 #define CONFIG_SYS_RMR 0
320 *-----------------------------------------------------------------------
321 * TMCNTSC - Time Counter Status and Control 4-40
322 *-----------------------------------------------------------------------
323 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
324 * and enable Time Counter
326 #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
329 *-----------------------------------------------------------------------
330 * PISCR - Periodic Interrupt Status and Control 4-42
331 *-----------------------------------------------------------------------
332 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
335 #define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
338 *-----------------------------------------------------------------------
339 * RCCR - RISC Controller Configuration 13-7
340 *-----------------------------------------------------------------------
342 #define CONFIG_SYS_RCCR 0
345 * Init Memory Controller:
347 * Bank Bus Machine PortSz Device
348 * ---- --- ------- ------ ------
349 * 0 60x GPCM 8 bit FLASH
350 * 1 60x SDRAM 32 bit SDRAM
351 * 3 60x GPCM 8 bit GPIO/PIGGY
352 * 5 60x GPCM 16 bit CFG-Flash
357 #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
362 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
368 #define CONFIG_SYS_MPTPR 0x1800
371 *-----------------------------------------------------------------------------
372 * Address for Mode Register Set (MRS) command
373 *-----------------------------------------------------------------------------
375 #define CONFIG_SYS_MRS_OFFS 0x00000110
376 #define CONFIG_SYS_PSRT 0x0e
378 #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
383 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1
386 * UPIO FPGA (GPIO/PIGGY) on CS3 initialization values
388 #define CONFIG_SYS_KMBEC_FPGA_BASE 0x30000000
389 #define CONFIG_SYS_KMBEC_FPGA_SIZE 128
391 #define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_KMBEC_FPGA_BASE & BRx_BA_MSK) |\
392 BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
394 #define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) |\
395 ORxG_CSNT | ORxG_ACS_DIV2 |\
396 ORxG_SCY_3_CLK | ORxG_TRLX)
399 * BFTICU board FPGA on CS4 initialization values
401 #define CONFIG_SYS_FPGA_BASE 0x40000000
402 #define CONFIG_SYS_FPGA_SIZE 1 /*1KB*/
404 #define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_FPGA_BASE & BRx_BA_MSK) |\
405 BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
407 #define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FPGA_SIZE << 10) |\
408 ORxG_CSNT | ORxG_ACS_DIV2 |\
409 ORxG_SCY_3_CLK | ORxG_TRLX)
412 * CFG-Flash on CS5 initialization values
414 #define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_FLASH_BASE_1 & BRx_BA_MSK) |\
415 BRx_PS_16 | BRx_MS_GPCM_P | BRx_V)
417 #define CONFIG_SYS_OR5_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE_1 + \
418 CONFIG_SYS_FLASH_SIZE_2) |\
419 ORxG_CSNT | ORxG_ACS_DIV2 |\
420 ORxG_SCY_5_CLK | ORxG_TRLX)
422 #define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
424 /* pass open firmware flat tree */
426 #define CONFIG_OF_LIBFDT 1
427 #define CONFIG_OF_BOARD_SETUP 1
429 #define OF_TBCLK (bd->bi_busfreq / 4)
430 #define OF_STDOUT_PATH "/soc/cpm/serial@11a90"
432 #endif /* __CONFIG_H */