ARMV7: AM3517/05: Add support for CraneBoard.
[oweals/u-boot.git] / include / configs / kilauea.h
1 /*
2  * Copyright (c) 2008 Nuovation System Designs, LLC
3  *   Grant Erickson <gerickson@nuovations.com>
4  *
5  * (C) Copyright 2007
6  * Stefan Roese, DENX Software Engineering, sr@denx.de.
7  *
8  * See file CREDITS for list of people who contributed to this
9  * project.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License as
13  * published by the Free Software Foundation; either version 2 of
14  * the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software
23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24  * MA 02111-1307 USA
25  */
26
27 /************************************************************************
28  * kilauea.h - configuration for AMCC Kilauea (405EX)
29  ***********************************************************************/
30
31 #ifndef __CONFIG_H
32 #define __CONFIG_H
33
34 /*-----------------------------------------------------------------------
35  * High Level Configuration Options
36  *----------------------------------------------------------------------*/
37 #define CONFIG_KILAUEA          1               /* Board is Kilauea     */
38 #define CONFIG_4xx              1               /* ... PPC4xx family    */
39 #define CONFIG_405EX            1               /* Specifc 405EX support*/
40 #define CONFIG_SYS_CLK_FREQ     33333333        /* ext frequency to pll */
41
42 #ifndef CONFIG_SYS_TEXT_BASE
43 #define CONFIG_SYS_TEXT_BASE    0xFFFA0000
44 #endif
45
46 /*
47  * Include common defines/options for all AMCC eval boards
48  */
49 #define CONFIG_HOSTNAME         kilauea
50 #include "amcc-common.h"
51
52 #define CONFIG_BOARD_EARLY_INIT_F 1             /* Call board_early_init_f */
53 #define CONFIG_MISC_INIT_R      1               /* Call misc_init_r     */
54 #define CONFIG_BOARD_TYPES
55 #define CONFIG_BOARD_EMAC_COUNT
56
57 /*-----------------------------------------------------------------------
58  * Base addresses -- Note these are effective addresses where the
59  * actual resources get mapped (not physical addresses)
60  *----------------------------------------------------------------------*/
61 #define CONFIG_SYS_FLASH_BASE           0xFC000000
62 #define CONFIG_SYS_NAND_ADDR            0xF8000000
63 #define CONFIG_SYS_FPGA_BASE            0xF0000000
64
65 /*-----------------------------------------------------------------------
66  * Initial RAM & Stack Pointer Configuration Options
67  *
68  *   There are traditionally three options for the primordial
69  *   (i.e. initial) stack usage on the 405-series:
70  *
71  *      1) On-chip Memory (OCM) (i.e. SRAM)
72  *      2) Data cache
73  *      3) SDRAM
74  *
75  *   For the 405EX(r), there is no OCM, so we are left with (2) or (3)
76  *   the latter of which is less than desireable since it requires
77  *   setting up the SDRAM and ECC in assembly code.
78  *
79  *   To use (2), define 'CONFIG_SYS_INIT_DCACHE_CS' to be an unused chip
80  *   select on the External Bus Controller (EBC) and then select a
81  *   value for 'CONFIG_SYS_INIT_RAM_ADDR' outside of the range of valid,
82  *   physical SDRAM. Otherwise, undefine 'CONFIG_SYS_INIT_DCACHE_CS' and
83  *   select a value for 'CONFIG_SYS_INIT_RAM_ADDR' within the range of valid,
84  *   physical SDRAM to use (3).
85  *-----------------------------------------------------------------------*/
86
87 #define CONFIG_SYS_INIT_DCACHE_CS       4
88
89 #if defined(CONFIG_SYS_INIT_DCACHE_CS)
90 #define CONFIG_SYS_INIT_RAM_ADDR        (CONFIG_SYS_SDRAM_BASE + ( 1 << 30))    /*  1 GiB */
91 #else
92 #define CONFIG_SYS_INIT_RAM_ADDR        (CONFIG_SYS_SDRAM_BASE + (32 << 20))    /* 32 MiB */
93 #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
94
95 #define CONFIG_SYS_INIT_RAM_SIZE        (4 << 10)                       /*  4 KiB */
96 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
97
98 /*
99  * If the data cache is being used for the primordial stack and global
100  * data area, the POST word must be placed somewhere else. The General
101  * Purpose Timer (GPT) is unused by u-boot and the kernel and preserves
102  * its compare and mask register contents across reset, so it is used
103  * for the POST word.
104  */
105
106 #if defined(CONFIG_SYS_INIT_DCACHE_CS)
107 # define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
108 # define CONFIG_SYS_POST_WORD_ADDR      (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
109 #else
110 # define CONFIG_SYS_INIT_EXTRA_SIZE     16
111 # define CONFIG_SYS_INIT_SP_OFFSET      (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_EXTRA_SIZE)
112 # define CONFIG_SYS_OCM_DATA_ADDR       CONFIG_SYS_INIT_RAM_ADDR
113 #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
114
115 /*-----------------------------------------------------------------------
116  * Serial Port
117  *----------------------------------------------------------------------*/
118 #define CONFIG_SYS_EXT_SERIAL_CLOCK     11059200        /* ext. 11.059MHz clk   */
119 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
120
121 /*-----------------------------------------------------------------------
122  * Environment
123  *----------------------------------------------------------------------*/
124 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
125 #define CONFIG_ENV_IS_IN_FLASH     1    /* use FLASH for environment vars       */
126 #else
127 #define CONFIG_ENV_IS_IN_NAND   1       /* use NAND for environment vars        */
128 #define CONFIG_ENV_IS_EMBEDDED  1       /* use embedded environment */
129 #endif
130
131 /*-----------------------------------------------------------------------
132  * FLASH related
133  *----------------------------------------------------------------------*/
134 #define CONFIG_SYS_FLASH_CFI                    /* The flash is CFI compatible  */
135 #define CONFIG_FLASH_CFI_DRIVER         /* Use common CFI driver        */
136
137 #define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE}
138 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
139 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max number of sectors on one chip    */
140
141 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
142 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
143
144 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)     */
145 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
146
147 #ifdef CONFIG_ENV_IS_IN_FLASH
148 #define CONFIG_ENV_SECT_SIZE    0x20000 /* size of one complete sector  */
149 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
150 #define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment Sector     */
151
152 /* Address and size of Redundant Environment Sector     */
153 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
154 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
155 #endif /* CONFIG_ENV_IS_IN_FLASH */
156
157 /*
158  * IPL (Initial Program Loader, integrated inside CPU)
159  * Will load first 4k from NAND (SPL) into cache and execute it from there.
160  *
161  * SPL (Secondary Program Loader)
162  * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
163  * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
164  * controller and the NAND controller so that the special U-Boot image can be
165  * loaded from NAND to SDRAM.
166  *
167  * NUB (NAND U-Boot)
168  * This NAND U-Boot (NUB) is a special U-Boot version which can be started
169  * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
170  *
171  * On 405EX the SPL is copied to SDRAM before the NAND controller is
172  * set up. While still running from location 0xfffff000...0xffffffff the
173  * NAND controller cannot be accessed since it is attached to CS0 too.
174  */
175 #define CONFIG_SYS_NAND_BOOT_SPL_SRC    0xfffff000      /* SPL location                 */
176 #define CONFIG_SYS_NAND_BOOT_SPL_SIZE   (4 << 10)       /* SPL size                     */
177 #define CONFIG_SYS_NAND_BOOT_SPL_DST    0x00800000      /* Copy SPL here                */
178 #define CONFIG_SYS_NAND_U_BOOT_DST      0x01000000      /* Load NUB to this addr        */
179 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr  */
180 #define CONFIG_SYS_NAND_BOOT_SPL_DELTA  (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
181
182 /*
183  * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
184  */
185 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (16 << 10)      /* Offset to RAM U-Boot image   */
186 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (384 << 10)     /* Size of RAM U-Boot image     */
187
188 /*
189  * Now the NAND chip has to be defined (no autodetection used!)
190  */
191 #define CONFIG_SYS_NAND_PAGE_SIZE       512             /* NAND chip page size          */
192 #define CONFIG_SYS_NAND_BLOCK_SIZE      (16 << 10)      /* NAND chip block size         */
193 #define CONFIG_SYS_NAND_PAGE_COUNT      32              /* NAND chip page count         */
194 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   5               /* Location of bad block marker */
195 #define CONFIG_SYS_NAND_4_ADDR_CYCLE    1               /* Fourth addr used (>32MB)     */
196
197 #define CONFIG_SYS_NAND_ECCSIZE 256
198 #define CONFIG_SYS_NAND_ECCBYTES        3
199 #define CONFIG_SYS_NAND_ECCSTEPS        (CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
200 #define CONFIG_SYS_NAND_OOBSIZE 16
201 #define CONFIG_SYS_NAND_ECCTOTAL        (CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS)
202 #define CONFIG_SYS_NAND_ECCPOS          {0, 1, 2, 3, 6, 7}
203
204 #ifdef CONFIG_ENV_IS_IN_NAND
205 /*
206  * For NAND booting the environment is embedded in the U-Boot image. Please take
207  * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
208  */
209 #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
210 #define CONFIG_ENV_OFFSET               (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
211 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
212 #endif
213
214 /*-----------------------------------------------------------------------
215  * NAND FLASH
216  *----------------------------------------------------------------------*/
217 #define CONFIG_SYS_MAX_NAND_DEVICE      1
218 #define CONFIG_SYS_NAND_BASE            (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
219 #define CONFIG_SYS_NAND_SELECT_DEVICE  1        /* nand driver supports mutipl. chips   */
220
221 /*-----------------------------------------------------------------------
222  * DDR SDRAM
223  *----------------------------------------------------------------------*/
224 #define CONFIG_SYS_MBYTES_SDRAM        (256)            /* 256MB                        */
225
226 /*
227  * CONFIG_PPC4xx_DDR_AUTOCALIBRATION
228  *
229  * Note: DDR Autocalibration Method_A scans the full range of possible PPC4xx
230  *       SDRAM Controller DDR autocalibration values and takes a lot longer
231  *       to run than Method_B.
232  * (See the Method_A and Method_B algorithm discription in the file:
233  *      arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c)
234  * Define CONFIG_PPC4xx_DDR_METHOD_A to use DDR autocalibration Method_A
235  *
236  * DDR Autocalibration Method_B is the default.
237  */
238 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
239 #define CONFIG_PPC4xx_DDR_AUTOCALIBRATION       /* IBM DDR autocalibration */
240 #define DEBUG_PPC4xx_DDR_AUTOCALIBRATION        /* dynamic DDR autocal debug */
241 #undef  CONFIG_PPC4xx_DDR_METHOD_A
242 #endif
243
244 #define CONFIG_SYS_SDRAM0_MB0CF_BASE    ((  0 << 20) + CONFIG_SYS_SDRAM_BASE)
245
246 /* DDR1/2 SDRAM Device Control Register Data Values */
247 #define CONFIG_SYS_SDRAM0_MB0CF ((CONFIG_SYS_SDRAM0_MB0CF_BASE >> 3)    | \
248                                  SDRAM_RXBAS_SDSZ_256MB         | \
249                                  SDRAM_RXBAS_SDAM_MODE7         | \
250                                  SDRAM_RXBAS_SDBE_ENABLE)
251 #define CONFIG_SYS_SDRAM0_MB1CF SDRAM_RXBAS_SDBE_DISABLE
252 #define CONFIG_SYS_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE
253 #define CONFIG_SYS_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE
254 #define CONFIG_SYS_SDRAM0_MCOPT1        (SDRAM_MCOPT1_PMU_OPEN          | \
255                                  SDRAM_MCOPT1_8_BANKS           | \
256                                  SDRAM_MCOPT1_DDR2_TYPE         | \
257                                  SDRAM_MCOPT1_QDEP              | \
258                                  SDRAM_MCOPT1_DCOO_DISABLED)
259 #define CONFIG_SYS_SDRAM0_MCOPT2        0x00000000
260 #define CONFIG_SYS_SDRAM0_MODT0 (SDRAM_MODT_EB0W_ENABLE | \
261                                  SDRAM_MODT_EB0R_ENABLE)
262 #define CONFIG_SYS_SDRAM0_MODT1 0x00000000
263 #define CONFIG_SYS_SDRAM0_CODT          (SDRAM_CODT_RK0R_ON             | \
264                                  SDRAM_CODT_CKLZ_36OHM          | \
265                                  SDRAM_CODT_DQS_1_8_V_DDR2      | \
266                                  SDRAM_CODT_IO_NMODE)
267 #define CONFIG_SYS_SDRAM0_RTR           SDRAM_RTR_RINT_ENCODE(1560)
268 #define CONFIG_SYS_SDRAM0_INITPLR0      (SDRAM_INITPLR_ENABLE                   | \
269                 SDRAM_INITPLR_IMWT_ENCODE(80)                           | \
270                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_NOP))
271 #define CONFIG_SYS_SDRAM0_INITPLR1      (SDRAM_INITPLR_ENABLE                   | \
272                 SDRAM_INITPLR_IMWT_ENCODE(3)                            | \
273                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE)          | \
274                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR)                   | \
275                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
276 #define CONFIG_SYS_SDRAM0_INITPLR2      (SDRAM_INITPLR_ENABLE                   | \
277                 SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
278                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
279                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR2)                 | \
280                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR2_TEMP_COMMERCIAL))
281 #define CONFIG_SYS_SDRAM0_INITPLR3      (SDRAM_INITPLR_ENABLE                   | \
282                 SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
283                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
284                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR3)                 | \
285                 SDRAM_INITPLR_IMA_ENCODE(0))
286 #define CONFIG_SYS_SDRAM0_INITPLR4      (SDRAM_INITPLR_ENABLE                   | \
287                 SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
288                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
289                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR)                  | \
290                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_DQS_DISABLE | \
291                                          JEDEC_MA_EMR_RTT_75OHM))
292 #define CONFIG_SYS_SDRAM0_INITPLR5      (SDRAM_INITPLR_ENABLE                   | \
293                 SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
294                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
295                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR)                   | \
296                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
297                                          JEDEC_MA_MR_CL_DDR2_4_0_CLK | \
298                                          JEDEC_MA_MR_BLEN_4 | \
299                                          JEDEC_MA_MR_DLL_RESET))
300 #define CONFIG_SYS_SDRAM0_INITPLR6      (SDRAM_INITPLR_ENABLE                   | \
301                 SDRAM_INITPLR_IMWT_ENCODE(3)                            | \
302                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE)          | \
303                 SDRAM_INITPLR_IBA_ENCODE(0x0)                           | \
304                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
305 #define CONFIG_SYS_SDRAM0_INITPLR7      (SDRAM_INITPLR_ENABLE                   | \
306                 SDRAM_INITPLR_IMWT_ENCODE(26)                           | \
307                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
308 #define CONFIG_SYS_SDRAM0_INITPLR8      (SDRAM_INITPLR_ENABLE                   | \
309                 SDRAM_INITPLR_IMWT_ENCODE(26)                           | \
310                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
311 #define CONFIG_SYS_SDRAM0_INITPLR9      (SDRAM_INITPLR_ENABLE                   | \
312                 SDRAM_INITPLR_IMWT_ENCODE(26)                           | \
313                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
314 #define CONFIG_SYS_SDRAM0_INITPLR10     (SDRAM_INITPLR_ENABLE                   | \
315                 SDRAM_INITPLR_IMWT_ENCODE(26)                           | \
316                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
317 #define CONFIG_SYS_SDRAM0_INITPLR11     (SDRAM_INITPLR_ENABLE                   | \
318                 SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
319                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
320                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR)                   | \
321                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
322                                          JEDEC_MA_MR_CL_DDR2_4_0_CLK | \
323                                          JEDEC_MA_MR_BLEN_4))
324 #define CONFIG_SYS_SDRAM0_INITPLR12     (SDRAM_INITPLR_ENABLE                   | \
325                 SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
326                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
327                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR)                  | \
328                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_ENTER | \
329                                          JEDEC_MA_EMR_RDQS_DISABLE | \
330                                          JEDEC_MA_EMR_DQS_DISABLE | \
331                                          JEDEC_MA_EMR_RTT_DISABLED | \
332                                          JEDEC_MA_EMR_ODS_NORMAL))
333 #define CONFIG_SYS_SDRAM0_INITPLR13     (SDRAM_INITPLR_ENABLE                   | \
334                 SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
335                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
336                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR)                  | \
337                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_EXIT | \
338                                          JEDEC_MA_EMR_RDQS_DISABLE | \
339                                          JEDEC_MA_EMR_DQS_DISABLE | \
340                                          JEDEC_MA_EMR_RTT_DISABLED | \
341                                          JEDEC_MA_EMR_ODS_NORMAL))
342 #define CONFIG_SYS_SDRAM0_INITPLR14     (SDRAM_INITPLR_DISABLE)
343 #define CONFIG_SYS_SDRAM0_INITPLR15     (SDRAM_INITPLR_DISABLE)
344 #define CONFIG_SYS_SDRAM0_RQDC          (SDRAM_RQDC_RQDE_ENABLE | \
345                                  SDRAM_RQDC_RQFD_ENCODE(56))
346 #define CONFIG_SYS_SDRAM0_RFDC          SDRAM_RFDC_RFFD_ENCODE(521)
347 #define CONFIG_SYS_SDRAM0_RDCC          (SDRAM_RDCC_RDSS_T2)
348 #define CONFIG_SYS_SDRAM0_DLCR          (SDRAM_DLCR_DCLM_AUTO           | \
349                                  SDRAM_DLCR_DLCS_CONT_DONE      | \
350                                  SDRAM_DLCR_DLCV_ENCODE(165))
351 #define CONFIG_SYS_SDRAM0_CLKTR (SDRAM_CLKTR_CLKP_180_DEG_ADV)
352 #define CONFIG_SYS_SDRAM0_WRDTR 0x00000000
353 #define CONFIG_SYS_SDRAM0_SDTR1 (SDRAM_SDTR1_LDOF_2_CLK | \
354                                  SDRAM_SDTR1_RTW_2_CLK  | \
355                                  SDRAM_SDTR1_RTRO_1_CLK)
356 #define CONFIG_SYS_SDRAM0_SDTR2 (SDRAM_SDTR2_RCD_3_CLK          | \
357                                  SDRAM_SDTR2_WTR_2_CLK          | \
358                                  SDRAM_SDTR2_XSNR_32_CLK        | \
359                                  SDRAM_SDTR2_WPC_4_CLK          | \
360                                  SDRAM_SDTR2_RPC_2_CLK          | \
361                                  SDRAM_SDTR2_RP_3_CLK           | \
362                                  SDRAM_SDTR2_RRD_2_CLK)
363 #define CONFIG_SYS_SDRAM0_SDTR3 (SDRAM_SDTR3_RAS_ENCODE(8)      | \
364                                  SDRAM_SDTR3_RC_ENCODE(11)      | \
365                                  SDRAM_SDTR3_XCS                | \
366                                  SDRAM_SDTR3_RFC_ENCODE(26))
367 #define CONFIG_SYS_SDRAM0_MMODE (SDRAM_MMODE_WR_DDR2_3_CYC | \
368                                  SDRAM_MMODE_DCL_DDR2_4_0_CLK | \
369                                  SDRAM_MMODE_BLEN_4)
370 #define CONFIG_SYS_SDRAM0_MEMODE        (SDRAM_MEMODE_DQS_DISABLE | \
371                                  SDRAM_MEMODE_RTT_75OHM)
372
373 /*-----------------------------------------------------------------------
374  * I2C
375  *----------------------------------------------------------------------*/
376 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address  */
377
378 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x52    /* I2C boot EEPROM (24C02BN)    */
379 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1       /* Bytes of address             */
380 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
381 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
382
383 /* I2C bootstrap EEPROM */
384 #define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR       0x52
385 #define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET     0
386 #define CONFIG_4xx_CONFIG_BLOCKSIZE             16
387
388 /* Standard DTT sensor configuration */
389 #define CONFIG_DTT_DS1775       1
390 #define CONFIG_DTT_SENSORS      { 0 }
391 #define CONFIG_SYS_I2C_DTT_ADDR 0x48
392
393 /* RTC configuration */
394 #define CONFIG_RTC_DS1338       1
395 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
396
397 /*-----------------------------------------------------------------------
398  * Ethernet
399  *----------------------------------------------------------------------*/
400 #define CONFIG_M88E1111_PHY     1
401 #define CONFIG_IBM_EMAC4_V4     1
402 #define CONFIG_EMAC_PHY_MODE    EMAC_PHY_MODE_RGMII_RGMII
403 #define CONFIG_PHY_ADDR         1       /* PHY address, See schematics  */
404
405 #define CONFIG_PHY_RESET        1       /* reset phy upon startup       */
406 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
407
408 #define CONFIG_HAS_ETH0         1
409
410 #define CONFIG_HAS_ETH1         1       /* add support for "eth1addr"   */
411 #define CONFIG_PHY1_ADDR        2
412
413 /* Debug messages for the DDR autocalibration */
414 #define CONFIG_AUTOCALIB                "silent\0"  /* default is non-verbose */
415
416 /*
417  * Default environment variables
418  */
419 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
420         CONFIG_AMCC_DEF_ENV                                             \
421         CONFIG_AMCC_DEF_ENV_POWERPC                                     \
422         CONFIG_AMCC_DEF_ENV_PPC_OLD                                     \
423         CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
424         CONFIG_AMCC_DEF_ENV_NAND_UPD                                    \
425         "logversion=2\0"                                                \
426         "kernel_addr=fc000000\0"                                        \
427         "fdt_addr=fc1e0000\0"                                           \
428         "ramdisk_addr=fc200000\0"                                       \
429         "pciconfighost=1\0"                                             \
430         "pcie_mode=RP:RP\0"                                             \
431         ""
432
433 /*
434  * Commands additional to the ones defined in amcc-common.h
435  */
436 #define CONFIG_CMD_CHIP_CONFIG
437 #define CONFIG_CMD_DATE
438 #define CONFIG_CMD_LOG
439 #define CONFIG_CMD_NAND
440 #define CONFIG_CMD_PCI
441 #define CONFIG_CMD_SNTP
442
443 /*
444  * Don't run the memory POST on the NAND-booting version. It will
445  * overwrite part of the U-Boot image which is already loaded from NAND
446  * to SDRAM.
447  */
448 #if defined(CONFIG_NAND_U_BOOT)
449 #define CONFIG_SYS_POST_MEMORY_ON       0
450 #else
451 #define CONFIG_SYS_POST_MEMORY_ON       CONFIG_SYS_POST_MEMORY
452 #endif
453
454 /* POST support */
455 #define CONFIG_POST             (CONFIG_SYS_POST_CACHE          | \
456                                  CONFIG_SYS_POST_CPU            | \
457                                  CONFIG_SYS_POST_ETHER          | \
458                                  CONFIG_SYS_POST_I2C            | \
459                                  CONFIG_SYS_POST_MEMORY_ON      | \
460                                  CONFIG_SYS_POST_UART)
461
462 /* Define here the base-addresses of the UARTs to test in POST */
463 #define CONFIG_SYS_POST_UART_TABLE      { CONFIG_SYS_NS16550_COM1, \
464                         CONFIG_SYS_NS16550_COM2 }
465
466 #define CONFIG_LOGBUFFER
467 #define CONFIG_SYS_POST_CACHE_ADDR      0x00800000 /* free virtual address      */
468
469 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
470
471 /*-----------------------------------------------------------------------
472  * PCI stuff
473  *----------------------------------------------------------------------*/
474 #define CONFIG_PCI                      /* include pci support          */
475 #define CONFIG_PCI_PNP          1       /* do pci plug-and-play         */
476 #define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup  */
477 #define CONFIG_PCI_CONFIG_HOST_BRIDGE
478
479 /*-----------------------------------------------------------------------
480  * PCIe stuff
481  *----------------------------------------------------------------------*/
482 #define CONFIG_SYS_PCIE_MEMBASE 0x90000000      /* mapped PCIe memory   */
483 #define CONFIG_SYS_PCIE_MEMSIZE 0x08000000      /* 128 Meg, smallest incr per port */
484
485 #define CONFIG_SYS_PCIE0_CFGBASE        0xa0000000      /* remote access */
486 #define CONFIG_SYS_PCIE0_XCFGBASE       0xb0000000      /* local access */
487 #define CONFIG_SYS_PCIE0_CFGMASK        0xe0000001      /* 512 Meg */
488
489 #define CONFIG_SYS_PCIE1_CFGBASE        0xc0000000      /* remote access */
490 #define CONFIG_SYS_PCIE1_XCFGBASE       0xd0000000      /* local access */
491 #define CONFIG_SYS_PCIE1_CFGMASK        0xe0000001      /* 512 Meg */
492
493 #define CONFIG_SYS_PCIE0_UTLBASE        0xef502000
494 #define CONFIG_SYS_PCIE1_UTLBASE        0xef503000
495
496 /* base address of inbound PCIe window */
497 #define CONFIG_SYS_PCIE_INBOUND_BASE    0x0000000000000000ULL
498
499 /*-----------------------------------------------------------------------
500  * External Bus Controller (EBC) Setup
501  *----------------------------------------------------------------------*/
502 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
503 /* booting from NAND, so NAND chips select has to be on CS 0 */
504 #define CONFIG_SYS_NAND_CS              0               /* NAND chip connected to CSx   */
505
506 /* Memory Bank 1 (NOR-FLASH) initialization                                     */
507 #define CONFIG_SYS_EBC_PB1AP            0x05806500
508 #define CONFIG_SYS_EBC_PB1CR           0xFC0DA000  /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit*/
509
510 /* Memory Bank 0 (NAND-FLASH) initialization                                    */
511 #define CONFIG_SYS_EBC_PB0AP            0x018003c0
512 #define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_NAND_ADDR | 0x1e000)
513 #else
514 #define CONFIG_SYS_NAND_CS              1               /* NAND chip connected to CSx   */
515
516 /* Memory Bank 0 (NOR-FLASH) initialization                                     */
517 #define CONFIG_SYS_EBC_PB0AP            0x05806500
518 #define CONFIG_SYS_EBC_PB0CR           0xFC0DA000  /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit*/
519
520 /* Memory Bank 1 (NAND-FLASH) initialization                                    */
521 #define CONFIG_SYS_EBC_PB1AP            0x018003c0
522 #define CONFIG_SYS_EBC_PB1CR            (CONFIG_SYS_NAND_ADDR | 0x1e000)
523 #endif
524
525 /* Memory Bank 2 (FPGA) initialization                                  */
526 #define CONFIG_SYS_EBC_PB2AP            (EBC_BXAP_BME_ENABLED |         \
527                                          EBC_BXAP_FWT_ENCODE(6) |       \
528                                          EBC_BXAP_BWT_ENCODE(1) |       \
529                                          EBC_BXAP_BCE_DISABLE |         \
530                                          EBC_BXAP_BCT_2TRANS |          \
531                                          EBC_BXAP_CSN_ENCODE(0) |       \
532                                          EBC_BXAP_OEN_ENCODE(0) |       \
533                                          EBC_BXAP_WBN_ENCODE(3) |       \
534                                          EBC_BXAP_WBF_ENCODE(1) |       \
535                                          EBC_BXAP_TH_ENCODE(4) |        \
536                                          EBC_BXAP_RE_DISABLED |         \
537                                          EBC_BXAP_SOR_DELAYED |         \
538                                          EBC_BXAP_BEM_WRITEONLY |       \
539                                          EBC_BXAP_PEN_DISABLED)
540 #define CONFIG_SYS_EBC_PB2CR    (CONFIG_SYS_FPGA_BASE | 0x18000)
541
542 #define CONFIG_SYS_EBC_CFG              0x7FC00000 /*  EBC0_CFG */
543
544 /*-----------------------------------------------------------------------
545  * GPIO Setup
546  *----------------------------------------------------------------------*/
547 #define CONFIG_SYS_4xx_GPIO_TABLE { /*    Out             GPIO  Alternate1      Alternate2      Alternate3 */ \
548 {                                                                                       \
549 /* GPIO Core 0 */                                                                       \
550 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO0 EBC_DATA_PAR(0)                 */      \
551 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO1 EBC_DATA_PAR(1)                 */      \
552 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO2 EBC_DATA_PAR(2)                 */      \
553 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO3 EBC_DATA_PAR(3)                 */      \
554 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO4 EBC_DATA(20)    USB2_DATA(4)    */      \
555 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO5 EBC_DATA(21)    USB2_DATA(5)    */      \
556 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO6 EBC_DATA(22)    USB2_DATA(6)    */      \
557 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO7 EBC_DATA(23)    USB2_DATA(7)    */      \
558 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 CS(1)/NFCE(1)   IRQ(7)          */      \
559 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 CS(2)/NFCE(2)   IRQ(8)          */      \
560 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 CS(3)/NFCE(3)  IRQ(9)          */      \
561 {GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 IRQ(6)                         */      \
562 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO12 EBC_DATA(16)   USB2_DATA(0)    */      \
563 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO13 EBC_DATA(17)   USB2_DATA(1)    */      \
564 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO14 EBC_DATA(18)   USB2_DATA(2)    */      \
565 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO15 EBC_DATA(19)   USB2_DATA(3)    */      \
566 {GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 UART0_DCD      UART1_CTS       */      \
567 {GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 UART0_DSR      UART1_RTS       */      \
568 {GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 UART0_CTS                      */      \
569 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 UART0_RTS                      */      \
570 {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO20 UART0_DTR      UART1_TX        */      \
571 {GPIO0_BASE, GPIO_IN,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO21 UART0_RI       UART1_RX        */      \
572 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO22 EBC_HOLD_REQ   DMA_ACK2        */      \
573 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO23 EBC_HOLD_ACK   DMA_REQ2        */      \
574 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO24 EBC_EXT_REQ    DMA_EOT2        IRQ(4) */ \
575 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO25 EBC_EXT_ACK    DMA_ACK3        IRQ(3) */ \
576 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 EBC_ADDR(5)    DMA_EOT0        TS(3) */ \
577 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO27 EBC_BUS_REQ    DMA_EOT3        IRQ(5) */ \
578 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO28                                */      \
579 {GPIO0_BASE, GPIO_IN,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO29 DMA_EOT1       IRQ(2)          */      \
580 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO30 DMA_REQ1       IRQ(1)          */      \
581 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO31 DMA_ACK1       IRQ(0)          */      \
582 }                                                                                               \
583 }
584
585 /*-----------------------------------------------------------------------
586  * Some Kilauea stuff..., mainly fpga registers
587  */
588 #define CONFIG_SYS_FPGA_REG_BASE                CONFIG_SYS_FPGA_BASE
589 #define CONFIG_SYS_FPGA_FIFO_BASE               (CONFIG_SYS_FPGA_BASE | (1 << 10))
590
591 /* interrupt */
592 #define CONFIG_SYS_FPGA_SLIC0_R_DPRAM_INT       0x80000000
593 #define CONFIG_SYS_FPGA_SLIC0_W_DPRAM_INT       0x40000000
594 #define CONFIG_SYS_FPGA_SLIC1_R_DPRAM_INT       0x20000000
595 #define CONFIG_SYS_FPGA_SLIC1_W_DPRAM_INT       0x10000000
596 #define CONFIG_SYS_FPGA_PHY0_INT                0x08000000
597 #define CONFIG_SYS_FPGA_PHY1_INT                0x04000000
598 #define CONFIG_SYS_FPGA_SLIC0_INT               0x02000000
599 #define CONFIG_SYS_FPGA_SLIC1_INT               0x01000000
600
601 /* DPRAM setting */
602 /* 00: 32B; 01: 64B; 10: 128B; 11: 256B  */
603 #define CONFIG_SYS_FPGA_DPRAM_R_INT_LINE        0x00400000      /* 64 B */
604 #define CONFIG_SYS_FPGA_DPRAM_W_INT_LINE        0x00100000      /* 64 B */
605 #define CONFIG_SYS_FPGA_DPRAM_RW_TYPE           0x00080000
606 #define CONFIG_SYS_FPGA_DPRAM_RST               0x00040000
607 #define CONFIG_SYS_FPGA_UART0_FO                0x00020000
608 #define CONFIG_SYS_FPGA_UART1_FO                0x00010000
609
610 /* loopback */
611 #define CONFIG_SYS_FPGA_CHIPSIDE_LOOPBACK       0x00004000
612 #define CONFIG_SYS_FPGA_LINESIDE_LOOPBACK       0x00008000
613 #define CONFIG_SYS_FPGA_SLIC0_ENABLE            0x00002000
614 #define CONFIG_SYS_FPGA_SLIC1_ENABLE            0x00001000
615 #define CONFIG_SYS_FPGA_SLIC0_CS                0x00000800
616 #define CONFIG_SYS_FPGA_SLIC1_CS                0x00000400
617 #define CONFIG_SYS_FPGA_USER_LED0               0x00000200
618 #define CONFIG_SYS_FPGA_USER_LED1               0x00000100
619
620 #define CONFIG_SYS_FPGA_MAGIC_MASK              0xffff0000
621 #define CONFIG_SYS_FPGA_MAGIC                   0xabcd0000
622 #define CONFIG_SYS_FPGA_VER_MASK                0x0000ff00
623
624 #endif  /* __CONFIG_H */