3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
5 * Configuation settings for the IXDP425 board.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 * High Level Configuration Options
33 #define CONFIG_IXP425 1 /* This is an IXP425 CPU */
34 #define CONFIG_IXDP425 1 /* on an IXDP425 Board */
36 /***************************************************************
37 * U-boot generic defines start here.
38 ***************************************************************/
40 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
43 * Size of malloc() pool
45 #define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
46 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
48 /* allow to overwrite serial and ethaddr */
49 #define CONFIG_ENV_OVERWRITE
51 #define CONFIG_BAUDRATE 115200
53 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_ELF | CFG_CMD_PCI)
56 #define CONFIG_NET_MULTI
57 #define CONFIG_EEPRO100
58 /* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */
59 /* These are u-boot generic parameters */
60 #include <cmd_confdefs.h>
62 #define CONFIG_BOOTDELAY 3
63 /*#define CONFIG_ETHADDR 08:00:3e:26:0a:5b*/
64 #define CONFIG_NETMASK 255.255.255.0
65 #define CONFIG_IPADDR 192.168.0.21
66 #define CONFIG_SERVERIP 192.168.0.148
67 #define CONFIG_BOOTCOMMAND "bootm 50040000"
68 #define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
69 #define CONFIG_CMDLINE_TAG
71 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
72 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
73 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
77 * Miscellaneous configurable options
79 #define CFG_LONGHELP /* undef to save memory */
80 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
81 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
82 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
83 #define CFG_MAXARGS 16 /* max number of command args */
84 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
86 #define CFG_MEMTEST_START 0x00400000 /* memtest works on */
87 #define CFG_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */
89 #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
91 #define CFG_LOAD_ADDR 0x00010000 /* default load address */
93 #define CFG_HZ 3333333 /* spec says 66.666 MHz, but it appears to be 33 */
95 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
100 * The stack sizes are set up in start.S using the settings below
102 #define CONFIG_STACKSIZE (128*1024) /* regular stack */
103 #ifdef CONFIG_USE_IRQ
104 #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
105 #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
108 /***************************************************************
109 * Platform/Board specific defines start here.
110 ***************************************************************/
118 * select serial console configuration
120 #define CFG_IXP425_CONSOLE IXP425_UART1 /* we use UART1 for console */
123 * Physical Memory Map
125 #define CONFIG_NR_DRAM_BANKS 1 /* we have 2 banks of DRAM */
126 #define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
127 #define PHYS_SDRAM_1_SIZE 0x01000000 /* 16 MB */
129 #define PHYS_FLASH_1 0x50000000 /* Flash Bank #1 */
130 #define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */
131 #define PHYS_FLASH_BANK_SIZE 0x00800000 /* 8 MB Banks */
132 #define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors (x1) */
134 #define CFG_DRAM_BASE 0x00000000
135 #define CFG_DRAM_SIZE 0x01000000
137 #define CFG_FLASH_BASE PHYS_FLASH_1
140 * Expansion bus settings
142 #define CFG_EXP_CS0 0xbcd23c42
147 #define CFG_SDR_CONFIG 0xd
148 #define CFG_SDR_MODE_CONFIG 0x1
149 #define CFG_SDRAM_REFRESH_CNT 0x81a
156 * FLASH and environment organization
158 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
159 #define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
161 /* timeout values are in ticks */
162 #define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */
163 #define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */
166 #define CFG_ENV_IS_IN_FLASH 1
167 #define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x20000) /* Addr of Environment Sector */
168 #define CFG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
170 #endif /* __CONFIG_H */