6 * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
8 * SPDX-License-Identifier: GPL-2.0+
15 * High Level Configuration Options
18 #define CONFIG_MPC5200
19 #define CONFIG_MPX5200 1 /* MPX5200 board */
20 #define CONFIG_MPC5200_DDR 1 /* use DDR RAM */
21 #define CONFIG_IPEK01 /* Motherboard is ipek01 */
22 #define CONFIG_DISPLAY_BOARDINFO
24 #define CONFIG_SYS_TEXT_BASE 0xfc000000
26 #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
28 #define CONFIG_MISC_INIT_R
30 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
31 #ifdef CONFIG_CMD_KGDB
32 #define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
36 * Serial console configuration
38 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
39 #define CONFIG_BAUDRATE 115200 /* ... at 9600 bps */
40 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
42 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
45 * Video configuration for LIME GDC
49 #define CONFIG_VIDEO_MB862xx
50 #define CONFIG_VIDEO_MB862xx_ACCEL
51 #define VIDEO_FB_16BPP_WORD_SWAP
52 #define CONFIG_CFB_CONSOLE
53 #define CONFIG_VIDEO_LOGO
54 #define CONFIG_VIDEO_BMP_LOGO
55 #define CONFIG_CONSOLE_EXTRA_INFO
56 #define CONFIG_VGA_AS_SINGLE_DEVICE
57 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
58 #define CONFIG_VIDEO_SW_CURSOR
59 #define CONFIG_SPLASH_SCREEN
60 #define CONFIG_VIDEO_BMP_GZIP
61 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */
62 /* Lime clock frequency */
63 #define CONFIG_SYS_MB862xx_CCF 0x90000 /* geo 166MHz other 133MHz */
65 #define CONFIG_SYS_MB862xx_MMR 0x41c767e3
70 * 0x40000000 - 0x4fffffff - PCI Memory
71 * 0x50000000 - 0x50ffffff - PCI IO Space
74 #define CONFIG_PCI_PNP 1
75 #define CONFIG_PCI_SCAN_SHOW 1
77 #define CONFIG_PCI_MEM_BUS 0x40000000
78 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
79 #define CONFIG_PCI_MEM_SIZE 0x10000000
81 #define CONFIG_PCI_IO_BUS 0x50000000
82 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
83 #define CONFIG_PCI_IO_SIZE 0x01000000
86 #define CONFIG_EEPRO100 1
87 #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
90 #define CONFIG_DOS_PARTITION
93 #define CONFIG_USB_OHCI_NEW
94 #define CONFIG_SYS_OHCI_BE_CONTROLLER
95 #define CONFIG_USB_STORAGE
97 #define CONFIG_SYS_USB_OHCI_CPU_INIT
98 #define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB
99 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200"
100 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
103 * Command line configuration.
106 #define CONFIG_CMD_BMP /* BMP support */
108 #define CONFIG_CMD_DATE /* support for RTC, date/time...*/
109 #define CONFIG_CMD_IDE /* IDE harddisk support */
110 #define CONFIG_CMD_IRQ /* irqinfo */
111 #define CONFIG_CMD_PCI /* pciinfo */
113 #define CONFIG_SYS_LOWBOOT 1
118 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
120 #define CONFIG_PREBOOT "echo;" \
121 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
124 #undef CONFIG_BOOTARGS
126 #define CONFIG_EXTRA_ENV_SETTINGS \
128 "consoledev=ttyPSC0\0" \
129 "hostname=ipek01\0" \
130 "nfsargs=setenv bootargs root=/dev/nfs rw " \
131 "nfsroot=${serverip}:${rootpath}\0" \
132 "ramargs=setenv bootargs root=/dev/ram rw\0" \
133 "addip=setenv bootargs ${bootargs} " \
134 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
135 ":${hostname}:${netdev}:off panic=1\0" \
136 "addtty=setenv bootargs ${bootargs} " \
137 "console=${consoledev},${baudrate}\0" \
138 "flash_nfs=run nfsargs addip addtty;" \
139 "bootm ${kernel_addr} - ${fdtaddr}\0" \
140 "flash_self=run ramargs addip addtty;" \
141 "bootm ${kernel_addr} ${ramdisk_addr} ${fdtaddr}\0" \
142 "net_nfs=tftp 200000 ${bootfile}; tftp ${fdtaddr} ${fdtfile};" \
143 "run nfsargs addip addtty;" \
144 "bootm ${loadaddr} - ${fdtaddr}\0" \
145 "rootpath=/opt/eldk/ppc_6xx\0" \
146 "bootfile=ipek01/uImage\0" \
147 "load=tftp 100000 ipek01/u-boot.bin\0" \
148 "update=protect off FC000000 +60000; era FC000000 +60000; " \
149 "cp.b 100000 FC000000 ${filesize}\0" \
150 "upd=run load;run update\0" \
152 "loadaddr=400000\0" \
153 "fdtfile=ipek01/ipek01.dtb\0" \
156 #define CONFIG_BOOTCOMMAND "run flash_self"
159 * IPB Bus clocking configuration.
161 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* for 133MHz */
162 /* PCI clock must be 33, because board will not boot */
163 #undef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* for 66MHz */
166 * Open firmware flat tree support
168 #define OF_CPU "PowerPC,5200@0"
169 #define OF_SOC "soc5200@f0000000"
170 #define OF_TBCLK (bd->bi_busfreq / 4)
175 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
176 #define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
178 #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
179 #define CONFIG_SYS_I2C_SLAVE 0x7F
182 * EEPROM configuration
184 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
185 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
186 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
187 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
192 #define CONFIG_RTC_PCF8563
193 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
195 #define CONFIG_SYS_FLASH_BASE 0xFC000000
196 #define CONFIG_SYS_FLASH_SIZE 0x01000000
197 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
198 CONFIG_SYS_MONITOR_LEN)
200 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
201 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
202 #define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
204 /* use CFI flash driver */
205 #define CONFIG_FLASH_CFI_DRIVER
206 #define CONFIG_SYS_FLASH_CFI
207 #define CONFIG_SYS_FLASH_EMPTY_INFO
208 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
211 * Environment settings
213 #define CONFIG_ENV_IS_IN_FLASH 1
214 #define CONFIG_ENV_SIZE 0x10000
215 #define CONFIG_ENV_SECT_SIZE 0x20000
216 #define CONFIG_ENV_OVERWRITE 1
217 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
218 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
223 #define CONFIG_SYS_MBAR 0xf0000000
224 #define CONFIG_SYS_SDRAM_BASE 0x00000000
225 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
226 #define CONFIG_SYS_SRAM_BASE 0xF1000000
227 #define CONFIG_SYS_SRAM_SIZE 0x00200000
228 #define CONFIG_SYS_LIME_BASE 0xE4000000
229 #define CONFIG_SYS_LIME_SIZE 0x04000000
230 #define CONFIG_SYS_FPGA_BASE 0xC0000000
231 #define CONFIG_SYS_FPGA_SIZE 0x10000000
232 #define CONFIG_SYS_MPEG_BASE 0xe2000000
233 #define CONFIG_SYS_MPEG_SIZE 0x01000000
234 #define CONFIG_SYS_CF_BASE 0xe1000000
235 #define CONFIG_SYS_CF_SIZE 0x01000000
237 /* Use SRAM until RAM will be available */
238 #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
239 /* End of used area in DPRAM */
240 #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
242 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
243 GENERATED_GBL_DATA_SIZE)
244 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
246 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
247 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
248 # define CONFIG_SYS_RAMBOOT 1
251 #define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
252 #define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 128 kB for malloc() */
253 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
256 * Ethernet configuration
258 #define CONFIG_MPC5xxx_FEC 1
259 #define CONFIG_MPC5xxx_FEC_MII100
260 #define CONFIG_PHY_ADDR 0x00
265 #define CONFIG_SYS_GPS_PORT_CONFIG 0x1d556624
268 * Miscellaneous configurable options
270 #define CONFIG_SYS_LONGHELP /* undef to save memory */
271 #ifdef CONFIG_CMD_KGDB
272 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
274 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
276 /* Print Buffer Size */
277 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
278 sizeof(CONFIG_SYS_PROMPT) + 16)
279 /* max number of command args */
280 #define CONFIG_SYS_MAXARGS 16
281 /* Boot Argument Buffer Size */
282 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
284 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
285 #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1...15 MB in DRAM */
287 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
290 * Various low-level settings
292 #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
293 #define CONFIG_SYS_HID0_FINAL HID0_ICE
295 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
296 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
297 #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
298 #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
299 #define CONFIG_SYS_CS1_START CONFIG_SYS_SRAM_BASE
300 #define CONFIG_SYS_CS1_SIZE CONFIG_SYS_SRAM_SIZE
301 #define CONFIG_SYS_CS3_START CONFIG_SYS_LIME_BASE
302 #define CONFIG_SYS_CS3_SIZE CONFIG_SYS_LIME_SIZE
303 #define CONFIG_SYS_CS6_START CONFIG_SYS_FPGA_BASE
304 #define CONFIG_SYS_CS6_SIZE CONFIG_SYS_FPGA_SIZE
305 #define CONFIG_SYS_CS5_START CONFIG_SYS_CF_BASE
306 #define CONFIG_SYS_CS5_SIZE CONFIG_SYS_CF_SIZE
307 #define CONFIG_SYS_CS7_START CONFIG_SYS_MPEG_BASE
308 #define CONFIG_SYS_CS7_SIZE CONFIG_SYS_MPEG_SIZE
310 #ifdef CONFIG_SYS_PCISPEED_66
311 #define CONFIG_SYS_BOOTCS_CFG 0x0006F900
312 #define CONFIG_SYS_CS1_CFG 0x0004FB00
313 #define CONFIG_SYS_CS2_CFG 0x0006F900
315 #define CONFIG_SYS_BOOTCS_CFG 0x0002F900
316 #define CONFIG_SYS_CS1_CFG 0x0001FB00
317 #define CONFIG_SYS_CS2_CFG 0x0002F90C
321 * Ack active, Muxed mode, AS=24 bit address, DS=32 bit data, 0
322 * waitstates, writeswap and readswap enabled
324 #define CONFIG_SYS_CS3_CFG 0x00FFFB0C
325 #define CONFIG_SYS_CS6_CFG 0x00FFFB0C
326 #define CONFIG_SYS_CS7_CFG 0x4040751C
328 #define CONFIG_SYS_CS_BURST 0x00000000
329 #define CONFIG_SYS_CS_DEADCYCLE 0x33330000
331 #define CONFIG_SYS_RESET_ADDRESS 0xff000000
333 /*-----------------------------------------------------------------------
335 *-----------------------------------------------------------------------
337 #define CONFIG_USB_CLOCK 0x0001BBBB
338 #define CONFIG_USB_CONFIG 0x00005000
340 /*-----------------------------------------------------------------------
341 * IDE/ATA stuff Supports IDE harddisk
342 *-----------------------------------------------------------------------
344 #define CONFIG_IDE_PREINIT
346 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
347 #define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
349 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
351 #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
353 /* Offset for data I/O */
354 #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
356 /* Offset for normal register accesses */
357 #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
359 /* Offset for alternate registers */
360 #define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
362 /* Interval between registers */
363 #define CONFIG_SYS_ATA_STRIDE 4
365 #endif /* __CONFIG_H */