2 * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
4 * U-Boot:include/configs/da850evm.h
6 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
8 * Based on davinci_dvevm.h. Original Copyrights follow:
10 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
12 * SPDX-License-Identifier: GPL-2.0+
21 #define CONFIG_DRIVER_TI_EMAC
22 #define CONFIG_BARIX_IPAM390
27 #define CONFIG_MACH_DAVINCI_DA850_EVM
28 #define CONFIG_ARM926EJS /* arm926ejs CPU core */
29 #define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
30 #define CONFIG_SOC_DA850 /* TI DA850 SoC */
31 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
32 #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
33 #define CONFIG_SYS_OSCIN_FREQ 24000000
34 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
35 #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
36 #define CONFIG_SYS_DA850_PLL_INIT
37 #define CONFIG_SYS_DA850_DDR_INIT
38 #define CONFIG_SYS_TEXT_BASE 0xc1080000
43 #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
44 #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
45 #define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */
46 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
48 /* memtest start addr */
49 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
51 /* memtest will be run on 16MB */
52 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 16 * 1024 * 1024)
54 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
56 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
57 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
58 DAVINCI_SYSCFG_SUSPSRC_UART2 | \
59 DAVINCI_SYSCFG_SUSPSRC_UART0 | \
60 DAVINCI_SYSCFG_SUSPSRC_EMAC)
65 #define CONFIG_SYS_DV_CLKMODE 0
66 #define CONFIG_SYS_DA850_PLL0_POSTDIV 1
67 #define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000
68 #define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001
69 #define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002
70 #define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003
71 #define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002
72 #define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1
73 #define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005
75 #define CONFIG_SYS_DA850_PLL1_POSTDIV 1
76 #define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000
77 #define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001
78 #define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002
80 #define CONFIG_SYS_DA850_PLL0_PLLM 24
81 #define CONFIG_SYS_DA850_PLL1_PLLM 24
84 * DDR2 memory configuration
86 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
87 DV_DDR_PHY_EXT_STRBEN | \
88 (0x2 << DV_DDR_PHY_RD_LATENCY_SHIFT))
89 #define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000498
91 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0x00000004
92 #define CONFIG_SYS_DA850_DDR2_PBBPR 0x00000020
95 #define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
96 (13 << DV_DDR_SDTMR1_RFC_SHIFT) | \
97 (2 << DV_DDR_SDTMR1_RP_SHIFT) | \
98 (2 << DV_DDR_SDTMR1_RCD_SHIFT) | \
99 (2 << DV_DDR_SDTMR1_WR_SHIFT) | \
100 (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \
101 (8 << DV_DDR_SDTMR1_RC_SHIFT) | \
102 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
103 (1 << DV_DDR_SDTMR1_WTR_SHIFT))
105 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
106 (8 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
107 (2 << DV_DDR_SDTMR2_XP_SHIFT) | \
108 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
109 (14 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
110 (0xc7 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
111 (1 << DV_DDR_SDTMR2_RTP_SHIFT) | \
112 (2 << DV_DDR_SDTMR2_CKE_SHIFT))
114 #define CONFIG_SYS_DA850_DDR2_SDBCR ( \
115 (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \
116 (1 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) | \
117 (1 << DV_DDR_SDCR_DDREN_SHIFT) | \
118 (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
119 (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
120 (2 << DV_DDR_SDCR_CL_SHIFT) | \
121 (3 << DV_DDR_SDCR_IBANK_SHIFT) | \
122 (2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
124 #define CONFIG_SYS_DA850_CS3CFG (DAVINCI_ABCR_WSETUP(2) | \
125 DAVINCI_ABCR_WSTROBE(2) | \
126 DAVINCI_ABCR_WHOLD(1) | \
127 DAVINCI_ABCR_RSETUP(1) | \
128 DAVINCI_ABCR_RSTROBE(4) | \
129 DAVINCI_ABCR_RHOLD(0) | \
130 DAVINCI_ABCR_TA(1) | \
131 DAVINCI_ABCR_ASIZE_8BIT)
137 #define CONFIG_SYS_NS16550
138 #define CONFIG_SYS_NS16550_SERIAL
139 #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
140 #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART0_BASE /* Base address of UART0 */
141 #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
142 #define CONFIG_CONS_INDEX 1 /* use UART0 for console */
143 #define CONFIG_BAUDRATE 115200 /* Default baud rate */
146 * Flash & Environment
148 #define CONFIG_NAND_DAVINCI
149 #define CONFIG_SYS_NO_FLASH
150 #define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
151 #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
152 #define CONFIG_ENV_SIZE (128 << 10)
153 #define CONFIG_SYS_NAND_USE_FLASH_BBT
154 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
155 #define CONFIG_SYS_NAND_PAGE_2K
156 #define CONFIG_SYS_NAND_CS 3
157 #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
158 #define CONFIG_SYS_NAND_MASK_CLE 0x10
159 #define CONFIG_SYS_NAND_MASK_ALE 0x8
160 #undef CONFIG_SYS_NAND_HW_ECC
161 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
162 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
163 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
164 #define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10)
165 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
166 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
167 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x120000
168 #define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
169 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
170 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
171 CONFIG_SYS_NAND_U_BOOT_SIZE - \
172 CONFIG_SYS_MALLOC_LEN - \
173 GENERATED_GBL_DATA_SIZE)
174 #define CONFIG_SYS_NAND_ECCPOS { \
175 24, 25, 26, 27, 28, \
176 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
177 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
178 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
180 #define CONFIG_SYS_NAND_PAGE_COUNT 64
181 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
182 #define CONFIG_SYS_NAND_ECCSIZE 512
183 #define CONFIG_SYS_NAND_ECCBYTES 10
184 #define CONFIG_SYS_NAND_OOBSIZE 64
185 #define CONFIG_SPL_NAND_SUPPORT
186 #define CONFIG_SPL_NAND_BASE
187 #define CONFIG_SPL_NAND_DRIVERS
188 #define CONFIG_SPL_NAND_ECC
189 #define CONFIG_SPL_NAND_SIMPLE
190 #define CONFIG_SPL_NAND_LOAD
193 * Network & Ethernet Configuration
195 #ifdef CONFIG_DRIVER_TI_EMAC
196 #define CONFIG_DRIVER_TI_EMAC_USE_RMII
197 #define CONFIG_BOOTP_DEFAULT
198 #define CONFIG_BOOTP_DNS
199 #define CONFIG_BOOTP_DNS2
200 #define CONFIG_BOOTP_SEND_HOSTNAME
201 #define CONFIG_NET_RETRY_COUNT 10
205 * U-Boot general configuration
207 #define CONFIG_MISC_INIT_R
208 #define CONFIG_BOARD_EARLY_INIT_F
209 #define CONFIG_BOOTFILE "uImage" /* Boot file name */
210 #define CONFIG_SYS_PROMPT "U-Boot > " /* Command Prompt */
211 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
212 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
213 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
214 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
215 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
216 #define CONFIG_VERSION_VARIABLE
217 #define CONFIG_AUTO_COMPLETE
218 #define CONFIG_SYS_HUSH_PARSER
219 #define CONFIG_CMDLINE_EDITING
220 #define CONFIG_SYS_LONGHELP
221 #define CONFIG_CRC32_VERIFY
222 #define CONFIG_MX_CYCLIC
227 #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
228 #define CONFIG_HWCONFIG /* enable hwconfig */
229 #define CONFIG_CMDLINE_TAG
230 #define CONFIG_REVISION_TAG
231 #define CONFIG_SETUP_MEMORY_TAGS
232 #define CONFIG_BOOTARGS \
233 "mem=128M console=ttyS0,115200n8 root=/dev/mtdblock0p4 rw noinitrd ip=dhcp"
234 #define CONFIG_BOOTDELAY 3
235 #define CONFIG_EXTRA_ENV_SETTINGS \
236 "hwconfig=dsp:wake=yes\0" \
237 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
238 "mtdids=" MTDIDS_DEFAULT "\0" \
239 "mtdparts=" MTDPARTS_DEFAULT "\0" \
240 "setbootparms=nand read c0100000 200000 400000;" \
241 "spl export atags c0100000;" \
242 "nand erase.part bootparms;" \
243 "nand write c0000100 180000 20000\0" \
249 #include <config_cmd_default.h>
250 #define CONFIG_CMD_ENV
251 #define CONFIG_CMD_ASKENV
252 #define CONFIG_CMD_DHCP
253 #define CONFIG_CMD_DIAG
254 #define CONFIG_CMD_MII
255 #define CONFIG_CMD_PING
256 #define CONFIG_CMD_SAVES
257 #define CONFIG_CMD_MEMORY
259 #ifdef CONFIG_CMD_BDI
260 #define CONFIG_CLOCKS
263 #ifndef CONFIG_DRIVER_TI_EMAC
264 #undef CONFIG_CMD_NET
265 #undef CONFIG_CMD_DHCP
266 #undef CONFIG_CMD_MII
267 #undef CONFIG_CMD_PING
270 #define CONFIG_CMD_NAND
271 #define CONFIG_CMD_NAND_TRIMFFS
273 #define CONFIG_CMD_MTDPARTS
274 #define CONFIG_MTD_DEVICE
275 #define CONFIG_MTD_PARTITIONS
277 #define CONFIG_RBTREE
278 #define CONFIG_CMD_UBI
279 #define CONFIG_CMD_UBIFS
281 #define MTDIDS_NAME_STR "davinci_nand.0"
282 #define MTDIDS_DEFAULT "nand0=" MTDIDS_NAME_STR
283 #define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \
284 "128k(u-boot-env)," \
287 "384k(factory-info)," \
291 /* defines for SPL */
293 #define CONFIG_SPL_FRAMEWORK
294 #define CONFIG_SPL_BOARD_INIT
295 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
296 CONFIG_SYS_MALLOC_LEN)
297 #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
298 #define CONFIG_SPL_SERIAL_SUPPORT
299 #define CONFIG_SPL_LIBCOMMON_SUPPORT
300 #define CONFIG_SPL_LIBGENERIC_SUPPORT
301 #define CONFIG_SPL_LDSCRIPT "board/$(BOARDDIR)/u-boot-spl-ipam390.lds"
302 #define CONFIG_SPL_STACK 0x8001ff00
303 #define CONFIG_SPL_TEXT_BASE 0x80000000
304 #define CONFIG_SPL_MAX_SIZE 0x20000
305 #define CONFIG_SPL_MAX_FOOTPRINT 32768
307 /* additions for new relocation code, must added to all boards */
308 #define CONFIG_SYS_SDRAM_BASE 0xc0000000
310 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
311 GENERATED_GBL_DATA_SIZE)
313 /* add FALCON boot mode */
314 #define CONFIG_CMD_SPL
315 #define CONFIG_SPL_OS_BOOT
316 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000
317 #define CONFIG_SYS_SPL_ARGS_ADDR LINUX_BOOT_PARAM_ADDR
318 #define CONFIG_CMD_SPL_NAND_OFS 0x00180000
319 #define CONFIG_CMD_SPL_WRITE_SIZE 0x400
322 #define CONFIG_SPL_GPIO_SUPPORT
323 #define CONFIG_DA8XX_GPIO
324 #define CONFIG_IPAM390_GPIO_BOOTMODE ((16 * 7) + 14)
326 #define CONFIG_SHOW_BOOT_PROGRESS
327 #define CONFIG_IPAM390_GPIO_LED_RED ((16 * 7) + 11)
328 #define CONFIG_IPAM390_GPIO_LED_GREEN ((16 * 7) + 12)
330 #endif /* __CONFIG_H */