2 * (C) Copyright 2000, 2001, 2002
3 * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de.
5 * Configuration for the Auerswald Innokom CPU board.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * include/configs/innokom.h - configuration options, board specific
34 * High Level Configuration Options
37 #define CONFIG_PXA250 1 /* This is an PXA250 CPU */
38 #define CONFIG_INNOKOM 1 /* on an Auerswald Innokom board */
40 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
41 /* for timer/console/ethernet */
43 /* we will never enable dcache, because we have to setup MMU first */
44 #define CONFIG_SYS_NO_DCACHE
51 * select serial console configuration
53 #define CONFIG_PXA_SERIAL
54 #define CONFIG_FFUART 1 /* we use FFUART on CSB226 */
56 /* allow to overwrite serial and ethaddr */
57 #define CONFIG_ENV_OVERWRITE
59 #define CONFIG_BAUDRATE 19200
60 #define CONFIG_MISC_INIT_R 1 /* we have a misc_init_r() function */
66 #define CONFIG_BOOTP_BOOTFILESIZE
67 #define CONFIG_BOOTP_BOOTPATH
68 #define CONFIG_BOOTP_GATEWAY
69 #define CONFIG_BOOTP_HOSTNAME
73 * Command line configuration.
76 #define CONFIG_CMD_ASKENV
77 #define CONFIG_CMD_BDI
78 #define CONFIG_CMD_CACHE
79 #define CONFIG_CMD_DHCP
80 #define CONFIG_CMD_ECHO
81 #define CONFIG_CMD_SAVEENV
82 #define CONFIG_CMD_FLASH
83 #define CONFIG_CMD_I2C
84 #define CONFIG_CMD_IMI
85 #define CONFIG_CMD_LOADB
86 #define CONFIG_CMD_MEMORY
87 #define CONFIG_CMD_NET
88 #define CONFIG_CMD_RUN
91 #define CONFIG_BOOTDELAY 3
92 /* #define CONFIG_BOOTARGS "root=/dev/nfs ip=bootp console=ttyS0,19200" */
93 #define CONFIG_BOOTARGS "console=ttyS0,19200"
94 #define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF
95 #define CONFIG_NETMASK 255.255.255.0
96 #define CONFIG_IPADDR 192.168.1.56
97 #define CONFIG_SERVERIP 192.168.1.2
98 #define CONFIG_BOOTCOMMAND "bootm 0x40000"
99 #define CONFIG_SHOW_BOOT_PROGRESS
101 #define CONFIG_CMDLINE_TAG 1
104 * Miscellaneous configurable options
108 * Size of malloc() pool
110 #define CONFIG_SYS_MALLOC_LEN (256*1024)
111 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
113 #define CONFIG_SYS_LONGHELP /* undef to save memory */
114 #define CONFIG_SYS_PROMPT "uboot> " /* Monitor Command Prompt */
115 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
116 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
117 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
118 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
120 #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
121 #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
123 #define CONFIG_SYS_LOAD_ADDR 0xa3000000 /* load kernel to this address */
125 #define CONFIG_SYS_HZ 1000
126 /* RS: the oscillator is actually 3680130?? */
128 #define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */
130 /* ^^^^^ Memory Speed 99.53 MHz */
131 /* ^^ Run Mode Speed = 2x Mem Speed */
132 /* ^^ Turbo Mode Sp. = 1x Run M. Sp. */
134 #define CONFIG_SYS_MONITOR_LEN 0x20000 /* 128 KiB */
136 /* valid baudrates */
137 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
142 #define CONFIG_HARD_I2C 1
143 #define CONFIG_SYS_I2C_SPEED 50000
144 #define CONFIG_SYS_I2C_SLAVE 0xfe
146 #define CONFIG_ENV_IS_IN_EEPROM 1
148 #define CONFIG_ENV_OFFSET 0x00 /* environment starts here */
149 #define CONFIG_ENV_SIZE 1024 /* 1 KiB */
150 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* A0 = 0 (hardwired) */
151 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 5 bits = 32 octets */
152 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 15 /* between stop and start */
153 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* length of address */
154 #define CONFIG_SYS_EEPROM_SIZE 4096 /* size in bytes */
155 #define CONFIG_SYS_I2C_INIT_BOARD 1 /* board has it's own init */
158 * SMSC91C111 Network Card
160 #define CONFIG_NET_MULTI
161 #define CONFIG_SMC91111 1
162 #define CONFIG_SMC91111_BASE 0x14000000 /* chip select 5 */
163 #undef CONFIG_SMC_USE_32_BIT /* 16 bit bus access */
164 #undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */
165 #define CONFIG_SMC_AUTONEG_TIMEOUT 10 /* timeout 10 seconds */
166 #undef CONFIG_SHOW_ACTIVITY
167 #define CONFIG_NET_RETRY_COUNT 10 /* # of retries */
172 * The stack sizes are set up in start.S using the settings below
174 #define CONFIG_STACKSIZE (128*1024) /* regular stack */
175 #ifdef CONFIG_USE_IRQ
176 #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
177 #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
181 * Physical Memory Map
183 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
184 #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
185 #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
187 #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
188 #define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */
190 #define CONFIG_SYS_DRAM_BASE 0xa0000000 /* RAM starts here */
191 #define CONFIG_SYS_DRAM_SIZE 0x04000000
193 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
195 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
196 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
202 /* development flash */
203 #define CONFIG_MTD_INNOKOM_16MB 1
204 #undef CONFIG_MTD_INNOKOM_64MB
206 /* production flash */
208 #define CONFIG_MTD_INNOKOM_64MB 1
209 #undef CONFIG_MTD_INNOKOM_16MB
212 /* No command line, one static partition, whole device */
213 #undef CONFIG_CMD_MTDPARTS
214 #define CONFIG_JFFS2_DEV "nor0"
215 #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
216 #define CONFIG_JFFS2_PART_OFFSET 0x00000000
218 /* mtdparts command line support */
219 /* Note: fake mtd_id used, no linux mtd map file */
221 #define CONFIG_CMD_MTDPARTS
222 #define MTDIDS_DEFAULT "nor0=innokom-0"
225 /* development flash */
227 #define MTDPARTS_DEFAULT "mtdparts=innokom-0:256k(uboot),768k(kernel),8m(user),7m(data)"
230 /* production flash */
232 #define MTDPARTS_DEFAULT "mtdparts=innokom-0:256k(uboot),768k(kernel),16256k(user1),16256k(user2),32m(data)"
247 * GP63 == TDM_OE is 1
252 #define CONFIG_SYS_GPSR0_VAL 0x03008000
253 #define CONFIG_SYS_GPSR1_VAL 0xC0028282
254 #define CONFIG_SYS_GPSR2_VAL 0x0001C000
256 /* GP02 == DON_RST is 0
258 * GP45 == USB_ACT is 0
261 * GP73 == SWUPD_LED is 0
263 #define CONFIG_SYS_GPCR0_VAL 0x00800004
264 #define CONFIG_SYS_GPCR1_VAL 0x30002000
265 #define CONFIG_SYS_GPCR2_VAL 0x00000100
267 /* GP00 == DON_READY is input
268 * GP01 == DON_OK is input
269 * GP02 == DON_RST is output
270 * GP03 == RESET_IND is input
271 * GP07 == RES11 is input
272 * GP09 == RES12 is input
273 * GP11 == SWUPDATE is input
274 * GP14 == nPOWEROK is input
275 * GP15 == nCS1 is output
276 * GP17 == RES22 is input
277 * GP18 == RDY is input
278 * GP23 == SCLK is output
279 * GP24 == SFRM is output
280 * GP25 == TXD is output
281 * GP26 == RXD is input
282 * GP32 == RES21 is input
283 * GP33 == nCS5 is output
284 * GP34 == FFRXD is input
285 * GP35 == CTS is input
286 * GP39 == FFTXD is output
287 * GP41 == RTS is output
288 * GP42 == USB_OK is input
289 * GP45 == USB_ACT is output
290 * GP46 == RXD is input
291 * GP47 == TXD is output
292 * GP49 == nPWE is output
293 * GP58 == nCPUBUSINT is input
294 * GP59 == LANINT is input
295 * GP60 == PLLEN is output
296 * GP61 == LED_A is output
297 * GP62 == LED_B is output
298 * GP63 == TDM_OE is output
299 * GP64 == nDSPINT is input
300 * GP65 == STRAP0 is input
301 * GP67 == STRAP1 is input
302 * GP69 == STRAP2 is input
303 * GP70 == STRAP3 is input
304 * GP71 == STRAP4 is input
305 * GP73 == SWUPD_LED is output
306 * GP78 == nCS2 is output
307 * GP79 == nCS3 is output
308 * GP80 == nCS4 is output
310 #define CONFIG_SYS_GPDR0_VAL 0x03808004
311 #define CONFIG_SYS_GPDR1_VAL 0xF002A282
312 #define CONFIG_SYS_GPDR2_VAL 0x0001C200
314 /* GP15 == nCS1 is AF10
315 * GP18 == RDY is AF01
316 * GP23 == SCLK is AF10
317 * GP24 == SFRM is AF10
318 * GP25 == TXD is AF10
319 * GP26 == RXD is AF01
320 * GP33 == nCS5 is AF10
321 * GP34 == FFRXD is AF01
322 * GP35 == CTS is AF01
323 * GP39 == FFTXD is AF10
324 * GP41 == RTS is AF10
325 * GP46 == RXD is AF10
326 * GP47 == TXD is AF01
327 * GP49 == nPWE is AF10
328 * GP78 == nCS2 is AF10
329 * GP79 == nCS3 is AF10
330 * GP80 == nCS4 is AF10
332 #define CONFIG_SYS_GAFR0_L_VAL 0x80000000
333 #define CONFIG_SYS_GAFR0_U_VAL 0x001A8010
334 #define CONFIG_SYS_GAFR1_L_VAL 0x60088058
335 #define CONFIG_SYS_GAFR1_U_VAL 0x00000008
336 #define CONFIG_SYS_GAFR2_L_VAL 0xA0000000
337 #define CONFIG_SYS_GAFR2_U_VAL 0x00000002
340 /* FIXME: set GPIO_RER/FER */
348 #define CONFIG_SYS_PSSR_VAL 0x37
353 * This is the configuration for nCS0/1 -> flash banks
354 * configuration for nCS1:
355 * [31] 0 - Slower Device
356 * [30:28] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns
357 * [27:24] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
358 * [23:20] 1011 - " for first access: (11+2)*MemClk = 130 ns
359 * [19] 1 - 16 Bit bus width
360 * [18:16] 000 - nonburst RAM or FLASH
361 * configuration for nCS0:
362 * [15] 0 - Slower Device
363 * [14:12] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns
364 * [11:08] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
365 * [07:04] 1011 - " for first access: (11+2)*MemClk = 130 ns
366 * [03] 1 - 16 Bit bus width
367 * [02:00] 000 - nonburst RAM or FLASH
369 #define CONFIG_SYS_MSC0_VAL 0x25b825b8 /* flash banks */
371 /* This is the configuration for nCS2/3 -> TDM-Switch, DSP
372 * configuration for nCS3: DSP
373 * [31] 0 - Slower Device
374 * [30:28] 001 - RRR3: CS deselect to CS time: 1*(2*MemClk) = 20 ns
375 * [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns
376 * [23:20] 0011 - RDF3: Address for first access: (3+1)*MemClk = 40 ns
377 * [19] 1 - 16 Bit bus width
378 * [18:16] 100 - variable latency I/O
379 * configuration for nCS2: TDM-Switch
380 * [15] 0 - Slower Device
381 * [14:12] 101 - RRR2: CS deselect to CS time: 5*(2*MemClk) = 100 ns
382 * [11:08] 1001 - RDN2: Address to data valid in bursts: (9+1)*MemClk = 100 ns
383 * [07:04] 0011 - RDF2: Address for first access: (3+1)*MemClk = 40 ns
384 * [03] 1 - 16 Bit bus width
385 * [02:00] 100 - variable latency I/O
387 #define CONFIG_SYS_MSC1_VAL 0x123C593C /* TDM switch, DSP */
389 /* This is the configuration for nCS4/5 -> ExtBus, LAN Controller
391 * configuration for nCS5: LAN Controller
392 * [31] 0 - Slower Device
393 * [30:28] 001 - RRR5: CS deselect to CS time: 1*(2*MemClk) = 20 ns
394 * [27:24] 0010 - RDN5: Address to data valid in bursts: (2+1)*MemClk = 30 ns
395 * [23:20] 0011 - RDF5: Address for first access: (3+1)*MemClk = 40 ns
396 * [19] 1 - 16 Bit bus width
397 * [18:16] 100 - variable latency I/O
398 * configuration for nCS4: ExtBus
399 * [15] 0 - Slower Device
400 * [14:12] 110 - RRR4: CS deselect to CS time: 6*(2*MemClk) = 120 ns
401 * [11:08] 1100 - RDN4: Address to data valid in bursts: (12+1)*MemClk = 130 ns
402 * [07:04] 1101 - RDF4: Address for first access: 13->(15+1)*MemClk = 160 ns
403 * [03] 1 - 16 Bit bus width
404 * [02:00] 100 - variable latency I/O
406 #define CONFIG_SYS_MSC2_VAL 0x123C6CDC /* extra bus, LAN controller */
408 /* MDCNFG: SDRAM Configuration Register
410 * [31:29] 000 - reserved
411 * [28] 0 - no SA1111 compatiblity mode
412 * [27] 0 - latch return data with return clock
413 * [26] 0 - alternate addressing for pair 2/3
414 * [25:24] 00 - timings
415 * [23] 0 - internal banks in lower partition 2/3 (not used)
416 * [22:21] 00 - row address bits for partition 2/3 (not used)
417 * [20:19] 00 - column address bits for partition 2/3 (not used)
418 * [18] 0 - SDRAM partition 2/3 width is 32 bit
419 * [17] 0 - SDRAM partition 3 disabled
420 * [16] 0 - SDRAM partition 2 disabled
421 * [15:13] 000 - reserved
422 * [12] 1 - SA1111 compatiblity mode
423 * [11] 1 - latch return data with return clock
424 * [10] 0 - no alternate addressing for pair 0/1
425 * [09:08] 01 - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk
426 * [7] 1 - 4 internal banks in lower partition pair
427 * [06:05] 10 - 13 row address bits for partition 0/1
428 * [04:03] 01 - 9 column address bits for partition 0/1
429 * [02] 0 - SDRAM partition 0/1 width is 32 bit
430 * [01] 0 - disable SDRAM partition 1
431 * [00] 1 - enable SDRAM partition 0
433 /* use the configuration above but disable partition 0 */
434 #define CONFIG_SYS_MDCNFG_VAL 0x000019c8
436 /* MDREFR: SDRAM Refresh Control Register
438 * [32:26] 0 - reserved
439 * [25] 0 - K2FREE: not free running
440 * [24] 0 - K1FREE: not free running
441 * [23] 1 - K0FREE: not free running
442 * [22] 0 - SLFRSH: self refresh disabled
444 * [20] 0 - APD: no auto power down
445 * [19] 0 - K2DB2: SDCLK2 is MemClk
446 * [18] 0 - K2RUN: disable SDCLK2
447 * [17] 0 - K1DB2: SDCLK1 is MemClk
448 * [16] 1 - K1RUN: enable SDCLK1
449 * [15] 1 - E1PIN: SDRAM clock enable
450 * [14] 1 - K0DB2: SDCLK0 is MemClk
451 * [13] 0 - K0RUN: disable SDCLK0
452 * [12] 1 - E0PIN: disable SDCKE0
453 * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24
455 #define CONFIG_SYS_MDREFR_VAL 0x0081D018
457 /* MDMRS: Mode Register Set Configuration Register
460 * [30:23] 00000000- MDMRS2: SDRAM2/3 MRS Value. (not used)
461 * [22:20] 000 - MDCL2: SDRAM2/3 Cas Latency. (not used)
462 * [19] 0 - MDADD2: SDRAM2/3 burst Type. Fixed to sequential. (not used)
463 * [18:16] 010 - MDBL2: SDRAM2/3 burst Length. Fixed to 4. (not used)
465 * [14:07] 00000000- MDMRS0: SDRAM0/1 MRS Value.
466 * [06:04] 010 - MDCL0: SDRAM0/1 Cas Latency.
467 * [03] 0 - MDADD0: SDRAM0/1 burst Type. Fixed to sequential.
468 * [02:00] 010 - MDBL0: SDRAM0/1 burst Length. Fixed to 4.
470 #define CONFIG_SYS_MDMRS_VAL 0x00020022
473 * PCMCIA and CF Interfaces
475 #define CONFIG_SYS_MECR_VAL 0x00000000
476 #define CONFIG_SYS_MCMEM0_VAL 0x00000000
477 #define CONFIG_SYS_MCMEM1_VAL 0x00000000
478 #define CONFIG_SYS_MCATT0_VAL 0x00000000
479 #define CONFIG_SYS_MCATT1_VAL 0x00000000
480 #define CONFIG_SYS_MCIO0_VAL 0x00000000
481 #define CONFIG_SYS_MCIO1_VAL 0x00000000
484 #define CSB226_USER_LED0 0x00000008
485 #define CSB226_USER_LED1 0x00000010
486 #define CSB226_USER_LED2 0x00000020
490 * FLASH and environment organization
492 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
493 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sect. on one chip */
495 /* timeout values are in ticks */
496 #define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
497 #define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
499 #endif /* __CONFIG_H */