2 * (C) Copyright 2000, 2001, 2002
3 * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de.
5 * Configuration for the Auerswald Innokom CPU board.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * include/configs/innokom.h - configuration options, board specific
36 * If we are developing, we might want to start U-Boot from ram
37 * so we MUST NOT initialize critical regs like mem-timing ...
39 #define CONFIG_INIT_CRITICAL /* undef for developing */
42 * High Level Configuration Options
45 #define CONFIG_PXA250 1 /* This is an PXA250 CPU */
46 #define CONFIG_INNOKOM 1 /* on an Auerswald Innokom board */
48 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
49 /* for timer/console/ethernet */
55 * select serial console configuration
57 #define CONFIG_FFUART 1 /* we use FFUART on CSB226 */
59 /* allow to overwrite serial and ethaddr */
60 #define CONFIG_ENV_OVERWRITE
62 #define CONFIG_BAUDRATE 19200
63 #define CONFIG_MISC_INIT_R 1 /* we have a misc_init_r() function */
65 #define CONFIG_COMMANDS (CFG_CMD_BDI|CFG_CMD_LOADB|CFG_CMD_IMI|CFG_CMD_FLASH|CFG_CMD_MEMORY|CFG_CMD_NET|CFG_CMD_ENV|CFG_CMD_RUN|CFG_CMD_ASKENV|CFG_CMD_ECHO|CFG_CMD_I2C|CFG_CMD_DHCP)
66 /* CONFIG_CMD_DFL|CFG_CMD_I2C|CFG_CMD_EEPROM|CFG_CMD_NET|CFG_CMD_JFFS2|CFG_CMD_DHCP) */
67 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
68 #include <cmd_confdefs.h>
70 #define CONFIG_BOOTDELAY 3
71 /* #define CONFIG_BOOTARGS "root=/dev/nfs ip=bootp console=ttyS0,19200" */
72 #define CONFIG_BOOTARGS "console=ttyS0,19200"
73 #define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF
74 #define CONFIG_NETMASK 255.255.255.0
75 #define CONFIG_IPADDR 192.168.1.56
76 #define CONFIG_SERVERIP 192.168.1.2
77 #define CONFIG_BOOTCOMMAND "bootm 0x40000"
78 #define CONFIG_SHOW_BOOT_PROGRESS
80 #define CONFIG_CMDLINE_TAG 1
83 * Miscellaneous configurable options
87 * Size of malloc() pool; this lives below the uppermost 128 KiB which are
88 * used for the RAM copy of the uboot code
91 #define CFG_MALLOC_LEN (256*1024)
93 #define CFG_LONGHELP /* undef to save memory */
94 #define CFG_PROMPT "uboot> " /* Monitor Command Prompt */
95 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
96 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
97 #define CFG_MAXARGS 16 /* max number of command args */
98 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
100 #define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
101 #define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
103 #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
105 #define CFG_LOAD_ADDR 0xa3000000 /* load kernel to this address */
107 #define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
108 /* RS: the oscillator is actually 3680130?? */
110 #define CFG_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */
112 /* ^^^^^ Memory Speed 99.53 MHz */
113 /* ^^ Run Mode Speed = 2x Mem Speed */
114 /* ^^ Turbo Mode Sp. = 1x Run M. Sp. */
116 #define CFG_MONITOR_LEN 0x20000 /* 128 KiB */
118 /* valid baudrates */
119 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
124 #define CONFIG_HARD_I2C 1
125 #define CFG_I2C_SPEED 50000
126 #define CFG_I2C_SLAVE 0xfe
128 #define CFG_ENV_IS_IN_EEPROM 1
130 #define CFG_ENV_OFFSET 0x00 /* environment starts here */
131 #define CFG_ENV_SIZE 1024 /* 1 KiB */
132 #define CFG_I2C_EEPROM_ADDR 0x50 /* A0 = 0 (hardwired) */
133 #define CFG_EEPROM_PAGE_WRITE_BITS 5 /* 5 bits = 32 octets */
134 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 15 /* between stop and start */
135 #define CFG_I2C_EEPROM_ADDR_LEN 2 /* length of address */
136 #define CFG_EEPROM_SIZE 4096 /* size in bytes */
137 #define CFG_I2C_INIT_BOARD 1 /* board has it's own init */
140 * SMSC91C111 Network Card
142 #define CONFIG_DRIVER_SMC91111 1
143 #define CONFIG_SMC91111_BASE 0x14000000 /* chip select 5 */
144 #undef CONFIG_SMC_USE_32_BIT /* 16 bit bus access */
145 #undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */
146 #undef CONFIG_SHOW_ACTIVITY
147 #define CONFIG_NET_RETRY_COUNT 10 /* # of retries */
152 * The stack sizes are set up in start.S using the settings below
154 #define CONFIG_STACKSIZE (128*1024) /* regular stack */
155 #ifdef CONFIG_USE_IRQ
156 #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
157 #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
161 * Physical Memory Map
163 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
164 #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
165 #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
167 #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
168 #define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */
170 #define CFG_DRAM_BASE 0xa0000000 /* RAM starts here */
171 #define CFG_DRAM_SIZE 0x04000000
173 #define CFG_FLASH_BASE PHYS_FLASH_1
179 #define CFG_JFFS_CUSTOM_PART 1 /* see board/innokom/flash.c */
180 #define CONFIG_MTD_INNOKOM_16MB 1 /* development flash */
181 #undef CONFIG_MTD_INNOKOM_64MB /* production flash */
196 * GP63 == TDM_OE is 1
201 #define CFG_GPSR0_VAL 0x03008000
202 #define CFG_GPSR1_VAL 0xC0028282
203 #define CFG_GPSR2_VAL 0x0001C000
205 /* GP02 == DON_RST is 0
207 * GP45 == USB_ACT is 0
210 * GP73 == SWUPD_LED is 0
212 #define CFG_GPCR0_VAL 0x00800004
213 #define CFG_GPCR1_VAL 0x30002000
214 #define CFG_GPCR2_VAL 0x00000100
216 /* GP00 == DON_READY is input
217 * GP01 == DON_OK is input
218 * GP02 == DON_RST is output
219 * GP03 == RESET_IND is input
220 * GP07 == RES11 is input
221 * GP09 == RES12 is input
222 * GP11 == SWUPDATE is input
223 * GP14 == nPOWEROK is input
224 * GP15 == nCS1 is output
225 * GP17 == RES22 is input
226 * GP18 == RDY is input
227 * GP23 == SCLK is output
228 * GP24 == SFRM is output
229 * GP25 == TXD is output
230 * GP26 == RXD is input
231 * GP32 == RES21 is input
232 * GP33 == nCS5 is output
233 * GP34 == FFRXD is input
234 * GP35 == CTS is input
235 * GP39 == FFTXD is output
236 * GP41 == RTS is output
237 * GP42 == USB_OK is input
238 * GP45 == USB_ACT is output
239 * GP46 == RXD is input
240 * GP47 == TXD is output
241 * GP49 == nPWE is output
242 * GP58 == nCPUBUSINT is input
243 * GP59 == LANINT is input
244 * GP60 == PLLEN is output
245 * GP61 == LED_A is output
246 * GP62 == LED_B is output
247 * GP63 == TDM_OE is output
248 * GP64 == nDSPINT is input
249 * GP65 == STRAP0 is input
250 * GP67 == STRAP1 is input
251 * GP69 == STRAP2 is input
252 * GP70 == STRAP3 is input
253 * GP71 == STRAP4 is input
254 * GP73 == SWUPD_LED is output
255 * GP78 == nCS2 is output
256 * GP79 == nCS3 is output
257 * GP80 == nCS4 is output
259 #define CFG_GPDR0_VAL 0x03808004
260 #define CFG_GPDR1_VAL 0xF002A282
261 #define CFG_GPDR2_VAL 0x0001C200
263 /* GP15 == nCS1 is AF10
264 * GP18 == RDY is AF01
265 * GP23 == SCLK is AF10
266 * GP24 == SFRM is AF10
267 * GP25 == TXD is AF10
268 * GP26 == RXD is AF01
269 * GP33 == nCS5 is AF10
270 * GP34 == FFRXD is AF01
271 * GP35 == CTS is AF01
272 * GP39 == FFTXD is AF10
273 * GP41 == RTS is AF10
274 * GP46 == RXD is AF10
275 * GP47 == TXD is AF01
276 * GP49 == nPWE is AF10
277 * GP78 == nCS2 is AF10
278 * GP79 == nCS3 is AF10
279 * GP80 == nCS4 is AF10
281 #define CFG_GAFR0_L_VAL 0x80000000
282 #define CFG_GAFR0_U_VAL 0x001A8010
283 #define CFG_GAFR1_L_VAL 0x60088058
284 #define CFG_GAFR1_U_VAL 0x00000008
285 #define CFG_GAFR2_L_VAL 0xA0000000
286 #define CFG_GAFR2_U_VAL 0x00000002
289 /* FIXME: set GPIO_RER/FER */
297 #define CFG_PSSR_VAL 0x37
302 * This is the configuration for nCS0/1 -> flash banks
303 * configuration for nCS1:
304 * [31] 0 - Slower Device
305 * [30:28] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns
306 * [27:24] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
307 * [23:20] 1011 - " for first access: (11+2)*MemClk = 130 ns
308 * [19] 1 - 16 Bit bus width
309 * [18:16] 000 - nonburst RAM or FLASH
310 * configuration for nCS0:
311 * [15] 0 - Slower Device
312 * [14:12] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns
313 * [11:08] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
314 * [07:04] 1011 - " for first access: (11+2)*MemClk = 130 ns
315 * [03] 1 - 16 Bit bus width
316 * [02:00] 000 - nonburst RAM or FLASH
318 #define CFG_MSC0_VAL 0x25b825b8 /* flash banks */
320 /* This is the configuration for nCS2/3 -> TDM-Switch, DSP
321 * configuration for nCS3: DSP
322 * [31] 0 - Slower Device
323 * [30:28] 001 - RRR3: CS deselect to CS time: 1*(2*MemClk) = 20 ns
324 * [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns
325 * [23:20] 0011 - RDF3: Address for first access: (3+1)*MemClk = 40 ns
326 * [19] 1 - 16 Bit bus width
327 * [18:16] 100 - variable latency I/O
328 * configuration for nCS2: TDM-Switch
329 * [15] 0 - Slower Device
330 * [14:12] 101 - RRR2: CS deselect to CS time: 5*(2*MemClk) = 100 ns
331 * [11:08] 1001 - RDN2: Address to data valid in bursts: (9+1)*MemClk = 100 ns
332 * [07:04] 0011 - RDF2: Address for first access: (3+1)*MemClk = 40 ns
333 * [03] 1 - 16 Bit bus width
334 * [02:00] 100 - variable latency I/O
336 #define CFG_MSC1_VAL 0x123C593C /* TDM switch, DSP */
338 /* This is the configuration for nCS4/5 -> ExtBus, LAN Controller
340 * configuration for nCS5: LAN Controller
341 * [31] 0 - Slower Device
342 * [30:28] 001 - RRR5: CS deselect to CS time: 1*(2*MemClk) = 20 ns
343 * [27:24] 0010 - RDN5: Address to data valid in bursts: (2+1)*MemClk = 30 ns
344 * [23:20] 0011 - RDF5: Address for first access: (3+1)*MemClk = 40 ns
345 * [19] 1 - 16 Bit bus width
346 * [18:16] 100 - variable latency I/O
347 * configuration for nCS4: ExtBus
348 * [15] 0 - Slower Device
349 * [14:12] 110 - RRR4: CS deselect to CS time: 6*(2*MemClk) = 120 ns
350 * [11:08] 1100 - RDN4: Address to data valid in bursts: (12+1)*MemClk = 130 ns
351 * [07:04] 1101 - RDF4: Address for first access: 13->(15+1)*MemClk = 160 ns
352 * [03] 1 - 16 Bit bus width
353 * [02:00] 100 - variable latency I/O
355 #define CFG_MSC2_VAL 0x123C6CDC /* extra bus, LAN controller */
357 /* MDCNFG: SDRAM Configuration Register
359 * [31:29] 000 - reserved
360 * [28] 0 - no SA1111 compatiblity mode
361 * [27] 0 - latch return data with return clock
362 * [26] 0 - alternate addressing for pair 2/3
363 * [25:24] 00 - timings
364 * [23] 0 - internal banks in lower partition 2/3 (not used)
365 * [22:21] 00 - row address bits for partition 2/3 (not used)
366 * [20:19] 00 - column address bits for partition 2/3 (not used)
367 * [18] 0 - SDRAM partition 2/3 width is 32 bit
368 * [17] 0 - SDRAM partition 3 disabled
369 * [16] 0 - SDRAM partition 2 disabled
370 * [15:13] 000 - reserved
371 * [12] 1 - SA1111 compatiblity mode
372 * [11] 1 - latch return data with return clock
373 * [10] 0 - no alternate addressing for pair 0/1
374 * [09:08] 01 - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk
375 * [7] 1 - 4 internal banks in lower partition pair
376 * [06:05] 10 - 13 row address bits for partition 0/1
377 * [04:03] 01 - 9 column address bits for partition 0/1
378 * [02] 0 - SDRAM partition 0/1 width is 32 bit
379 * [01] 0 - disable SDRAM partition 1
380 * [00] 1 - enable SDRAM partition 0
382 /* use the configuration above but disable partition 0 */
383 #define CFG_MDCNFG_VAL 0x000019c8
385 /* MDREFR: SDRAM Refresh Control Register
387 * [32:26] 0 - reserved
388 * [25] 0 - K2FREE: not free running
389 * [24] 0 - K1FREE: not free running
390 * [23] 1 - K0FREE: not free running
391 * [22] 0 - SLFRSH: self refresh disabled
393 * [20] 0 - APD: no auto power down
394 * [19] 0 - K2DB2: SDCLK2 is MemClk
395 * [18] 0 - K2RUN: disable SDCLK2
396 * [17] 0 - K1DB2: SDCLK1 is MemClk
397 * [16] 1 - K1RUN: enable SDCLK1
398 * [15] 1 - E1PIN: SDRAM clock enable
399 * [14] 1 - K0DB2: SDCLK0 is MemClk
400 * [13] 0 - K0RUN: disable SDCLK0
401 * [12] 1 - E0PIN: disable SDCKE0
402 * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24
404 #define CFG_MDREFR_VAL 0x0081D018
406 /* MDMRS: Mode Register Set Configuration Register
409 * [30:23] 00000000- MDMRS2: SDRAM2/3 MRS Value. (not used)
410 * [22:20] 000 - MDCL2: SDRAM2/3 Cas Latency. (not used)
411 * [19] 0 - MDADD2: SDRAM2/3 burst Type. Fixed to sequential. (not used)
412 * [18:16] 010 - MDBL2: SDRAM2/3 burst Length. Fixed to 4. (not used)
414 * [14:07] 00000000- MDMRS0: SDRAM0/1 MRS Value.
415 * [06:04] 010 - MDCL0: SDRAM0/1 Cas Latency.
416 * [03] 0 - MDADD0: SDRAM0/1 burst Type. Fixed to sequential.
417 * [02:00] 010 - MDBL0: SDRAM0/1 burst Length. Fixed to 4.
419 #define CFG_MDMRS_VAL 0x00020022
422 * PCMCIA and CF Interfaces
424 #define CFG_MECR_VAL 0x00000000
425 #define CFG_MCMEM0_VAL 0x00000000
426 #define CFG_MCMEM1_VAL 0x00000000
427 #define CFG_MCATT0_VAL 0x00000000
428 #define CFG_MCATT1_VAL 0x00000000
429 #define CFG_MCIO0_VAL 0x00000000
430 #define CFG_MCIO1_VAL 0x00000000
433 #define CSB226_USER_LED0 0x00000008
434 #define CSB226_USER_LED1 0x00000010
435 #define CSB226_USER_LED2 0x00000020
439 * FLASH and environment organization
441 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
442 #define CFG_MAX_FLASH_SECT 128 /* max number of sect. on one chip */
444 /* timeout values are in ticks */
445 #define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
446 #define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
448 #endif /* __CONFIG_H */