2 * (C) Copyright 2003-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * High Level Configuration Options
32 #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
33 #define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
34 #define CONFIG_INKA4X0 1 /* INKA4x0 board */
36 #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
38 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
39 #define BOOTFLAG_WARM 0x02 /* Software reboot */
41 #define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
42 #define CONFIG_MISC_INIT_R 1 /* Use misc_init_r() */
44 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
47 * Serial console configuration
49 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
50 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
51 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
55 * 0x40000000 - 0x4fffffff - PCI Memory
56 * 0x50000000 - 0x50ffffff - PCI IO Space
59 #define CONFIG_PCI_PNP 1
60 #define CONFIG_PCI_SCAN_SHOW 1
61 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
63 #define CONFIG_PCI_MEM_BUS 0x40000000
64 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
65 #define CONFIG_PCI_MEM_SIZE 0x10000000
67 #define CONFIG_PCI_IO_BUS 0x50000000
68 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
69 #define CONFIG_PCI_IO_SIZE 0x01000000
71 #define CONFIG_SYS_XLB_PIPELINING 1
74 #define CONFIG_MAC_PARTITION
75 #define CONFIG_DOS_PARTITION
76 #define CONFIG_ISO_PARTITION
82 #define CONFIG_BOOTP_BOOTFILESIZE
83 #define CONFIG_BOOTP_BOOTPATH
84 #define CONFIG_BOOTP_GATEWAY
85 #define CONFIG_BOOTP_HOSTNAME
89 * Command line configuration.
91 #include <config_cmd_default.h>
93 #define CONFIG_CMD_DHCP
94 #define CONFIG_CMD_EXT2
95 #define CONFIG_CMD_FAT
96 #define CONFIG_CMD_IDE
97 #define CONFIG_CMD_NFS
98 #define CONFIG_CMD_PCI
99 #define CONFIG_CMD_SNTP
100 #define CONFIG_CMD_USB
103 #define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
105 #if (TEXT_BASE == 0xFFE00000) /* Boot low */
106 # define CONFIG_SYS_LOWBOOT 1
112 #define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
114 #define CONFIG_PREBOOT "echo;" \
115 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
118 #undef CONFIG_BOOTARGS
120 #define CONFIG_ETHADDR 00:a0:a4:03:00:00
121 #define CONFIG_OVERWRITE_ETHADDR_ONCE
123 #define CONFIG_IPADDR 192.168.100.2
124 #define CONFIG_SERVERIP 192.168.100.1
125 #define CONFIG_NETMASK 255.255.255.0
126 #define HOSTNAME inka4x0
127 #define CONFIG_BOOTFILE /tftpboot/inka4x0/uImage
128 #define CONFIG_ROOTPATH /opt/eldk/ppc_6xx
130 #define CONFIG_EXTRA_ENV_SETTINGS \
132 "nfsargs=setenv bootargs root=/dev/nfs rw " \
133 "nfsroot=${serverip}:${rootpath}\0" \
134 "ramargs=setenv bootargs root=/dev/ram rw\0" \
135 "addip=setenv bootargs ${bootargs} " \
136 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
137 ":${hostname}:${netdev}:off panic=1\0" \
138 "addcons=setenv bootargs ${bootargs} " \
139 "console=ttyS0,${baudrate}\0" \
140 "flash_nfs=run nfsargs addip addcons;" \
141 "bootm ${kernel_addr}\0" \
142 "net_nfs=tftp 200000 ${bootfile};" \
143 "run nfsargs addip addcons;bootm\0" \
144 "enable_disp=mw.l 100000 04000000 1;" \
145 "cp.l 100000 f0000b20 1;" \
146 "cp.l 100000 f0000b28 1\0" \
147 "ideargs=setenv bootargs root=/dev/hda1 rw\0" \
148 "ide_boot=ext2load ide 0:1 200000 uImage;" \
149 "run ideargs addip addcons enable_disp;bootm\0" \
153 #define CONFIG_BOOTCOMMAND "run ide_boot"
156 * IPB Bus clocking configuration.
158 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
161 * Flash configuration
163 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
164 #define CONFIG_FLASH_CFI_DRIVER 1
165 #define CONFIG_SYS_FLASH_BASE 0xffe00000
166 #define CONFIG_SYS_FLASH_SIZE 0x00200000
167 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
168 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
169 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
170 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
173 * Environment settings
175 #define CONFIG_ENV_IS_IN_FLASH 1
176 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000)
177 #define CONFIG_ENV_SIZE 0x2000
178 #define CONFIG_ENV_SECT_SIZE 0x2000
179 #define CONFIG_ENV_OVERWRITE 1
180 #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
185 #define CONFIG_SYS_MBAR 0xF0000000
186 #define CONFIG_SYS_SDRAM_BASE 0x00000000
187 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
190 * SDRAM controller configuration
192 #undef CONFIG_SDR_MT48LC16M16A2
193 #undef CONFIG_DDR_MT46V16M16
194 #undef CONFIG_DDR_MT46V32M16
195 #undef CONFIG_DDR_HYB25D512160BF
196 #define CONFIG_DDR_K4H511638C
198 /* Use ON-Chip SRAM until RAM will be available */
199 #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
201 /* preserve space for the post_word at end of on-chip SRAM */
202 #define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
204 #define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
208 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
209 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
210 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
212 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE
213 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
214 # define CONFIG_SYS_RAMBOOT 1
217 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
218 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
219 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
222 * Ethernet configuration
224 #define CONFIG_MPC5xxx_FEC 1
225 #define CONFIG_MPC5xxx_FEC_MII100
227 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
229 /* #define CONFIG_MPC5xxx_FEC_MII10 */
230 #define CONFIG_PHY_ADDR 0x00
236 * use CS1 as gpio_wkup_6 output
237 * Bit 0 (mask: 0x80000000): 0
238 * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
239 * 00 -> No Alternatives, I2C1 is used for onboard EEPROM
240 * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1 do not use on TQM5200 with onboard
242 * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
243 * use PSC6_1 and PSC6_3 as GPIO: Bits 9:11 (mask: 0x07000000):
244 * 011 -> PSC6 could not be used as UART or CODEC. IrDA still possible.
246 #define CONFIG_SYS_GPS_PORT_CONFIG 0x01001004
251 #define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
254 * Miscellaneous configurable options
256 #define CONFIG_SYS_LONGHELP /* undef to save memory */
257 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
258 #if defined(CONFIG_CMD_KGDB)
259 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
261 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
263 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
264 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
265 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
267 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
268 #if defined(CONFIG_CMD_KGDB)
269 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
272 /* Enable an alternate, more extensive memory test */
273 #define CONFIG_SYS_ALT_MEMTEST
275 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
276 #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
278 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
280 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
283 * Enable loopw command.
288 * Various low-level settings
290 #if defined(CONFIG_MPC5200)
291 #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
292 #define CONFIG_SYS_HID0_FINAL HID0_ICE
294 #define CONFIG_SYS_HID0_INIT 0
295 #define CONFIG_SYS_HID0_FINAL 0
298 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
299 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
300 #define CONFIG_SYS_BOOTCS_CFG 0x00087800 /* for pci_clk = 66 MHz */
301 #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
302 #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
304 /* 32Mbit SRAM @0x30000000 */
305 #define CONFIG_SYS_CS1_START 0x30000000
306 #define CONFIG_SYS_CS1_SIZE 0x00400000
307 #define CONFIG_SYS_CS1_CFG 0x31800 /* for pci_clk = 33 MHz */
309 /* 2 quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */
310 #define CONFIG_SYS_CS2_START 0x80000000
311 #define CONFIG_SYS_CS2_SIZE 0x0001000
312 #define CONFIG_SYS_CS2_CFG 0x21800 /* for pci_clk = 33 MHz */
314 /* GPIO in @0x30400000 */
315 #define CONFIG_SYS_CS3_START 0x30400000
316 #define CONFIG_SYS_CS3_SIZE 0x00100000
317 #define CONFIG_SYS_CS3_CFG 0x31800 /* for pci_clk = 33 MHz */
319 #define CONFIG_SYS_CS_BURST 0x00000000
320 #define CONFIG_SYS_CS_DEADCYCLE 0x33333333
322 /*-----------------------------------------------------------------------
324 *-----------------------------------------------------------------------
326 #define CONFIG_USB_OHCI
327 #define CONFIG_USB_CLOCK 0x00015555
328 #define CONFIG_USB_CONFIG 0x00001000
329 #define CONFIG_USB_STORAGE
331 /*-----------------------------------------------------------------------
332 * IDE/ATA stuff Supports IDE harddisk
333 *-----------------------------------------------------------------------
336 #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
338 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
339 #undef CONFIG_IDE_LED /* LED for ide not supported */
341 #define CONFIG_IDE_RESET /* reset for ide supported */
342 #define CONFIG_IDE_PREINIT
344 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
345 #define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */
347 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
348 #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
349 #define CONFIG_SYS_ATA_DATA_OFFSET 0x0060 /* Offset for data I/O */
350 #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) /* Offset for normal register accesses */
351 #define CONFIG_SYS_ATA_ALT_OFFSET 0x005C /* Offset for alternate registers */
352 #define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
354 #define CONFIG_ATAPI 1
356 #define CONFIG_SYS_BRIGHTNESS 0xFF /* LCD Default Brightness (255 = off) */
358 #endif /* __CONFIG_H */