include/configs/ids8313.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2013
   4  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   5  *
   6  * Based on:
   7  * Copyright (c) 2011 IDS GmbH, Germany
   8  * Sergej Stepanov <ste@ids.de>
   9  */
  10
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 /*
  15  * High Level Configuration Options
  16  */
  17 #define CONFIG_FSL_ELBC
  18
  19 #define CONFIG_BOOT_RETRY_TIME          900
  20 #define CONFIG_BOOT_RETRY_MIN           30
  21 #define CONFIG_RESET_TO_RETRY
  22
  23 #define CONFIG_SYS_IMMR         0xF0000000
  24
  25 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
  26 #define CONFIG_SYS_ACR_RPTCNT           3       /* Arbiter repeat count (0-7) */
  27
  28 #define CONFIG_SYS_SICRH        0x00000000
  29 #define CONFIG_SYS_SICRL        (SICRL_LBC | SICRL_SPI_D)
  30
  31 #define CONFIG_HWCONFIG
  32
  33 #define CONFIG_SYS_HID0_INIT    0x000000000
  34 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK |\
  35                                  HID0_ENABLE_INSTRUCTION_CACHE |\
  36                                  HID0_DISABLE_DYNAMIC_POWER_MANAGMENT)
  37
  38 #define CONFIG_SYS_HID2 (HID2_HBE | 0x00020000)
  39
  40 /*
  41  * Definitions for initial stack pointer and data area (in DCACHE )
  42  */
  43 #define CONFIG_SYS_INIT_RAM_LOCK
  44 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000
  45 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* End of used area in DPRAM */
  46 #define CONFIG_SYS_GBL_DATA_SIZE        0x100
  47 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE \
  48                                          - CONFIG_SYS_GBL_DATA_SIZE)
  49 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
  50
  51 /*
  52  * Local Bus LCRR and LBCR regs
  53  */
  54 #define CONFIG_SYS_LCRR_EADC            LCRR_EADC_1
  55 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
  56 #define CONFIG_SYS_LBC_LBCR             (0x00040000 |\
  57                                          (0xFF << LBCR_BMT_SHIFT) |\
  58                                          0xF)
  59
  60 #define CONFIG_SYS_LBC_MRTPR            0x20000000
  61
  62 /*
  63  * Internal Definitions
  64  */
  65 /*
  66  * DDR Setup
  67  */
  68 #define CONFIG_SYS_DDR_BASE             0x00000000
  69 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  70 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  71
  72 /*
  73  * Manually set up DDR parameters,
  74  * as this board has not the SPD connected to I2C.
  75  */
  76 #define CONFIG_SYS_DDR_SIZE             256             /* MB */
  77 #define CONFIG_SYS_DDR_CONFIG           (CSCONFIG_EN |\
  78                                          0x00010000 |\
  79                                          CSCONFIG_ROW_BIT_13 |\
  80                                          CSCONFIG_COL_BIT_10)
  81
  82 #define CONFIG_SYS_DDR_CONFIG_256       (CONFIG_SYS_DDR_CONFIG | \
  83                                          CSCONFIG_BANK_BIT_3)
  84
  85 #define CONFIG_SYS_DDR_TIMING_3 (1 << 16)       /* ext refrec */
  86 #define CONFIG_SYS_DDR_TIMING_0 ((3 << TIMING_CFG0_RWT_SHIFT) |\
  87                                 (3 << TIMING_CFG0_WRT_SHIFT) |\
  88                                 (3 << TIMING_CFG0_RRT_SHIFT) |\
  89                                 (3 << TIMING_CFG0_WWT_SHIFT) |\
  90                                 (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) |\
  91                                 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) |\
  92                                 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
  93                                 (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  94 #define CONFIG_SYS_DDR_TIMING_1 ((4 << TIMING_CFG1_PRETOACT_SHIFT) |\
  95                                 (12 << TIMING_CFG1_ACTTOPRE_SHIFT) |\
  96                                 (4 << TIMING_CFG1_ACTTORW_SHIFT) |\
  97                                 (7 << TIMING_CFG1_CASLAT_SHIFT) |\
  98                                 (4 << TIMING_CFG1_REFREC_SHIFT) |\
  99                                 (4 << TIMING_CFG1_WRREC_SHIFT) |\
 100                                 (2 << TIMING_CFG1_ACTTOACT_SHIFT) |\
 101                                 (2 << TIMING_CFG1_WRTORD_SHIFT))
 102 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) |\
 103                                 (5 << TIMING_CFG2_CPO_SHIFT) |\
 104                                 (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) |\
 105                                 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) |\
 106                                 (0 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) |\
 107                                 (1 << TIMING_CFG2_CKE_PLS_SHIFT) |\
 108                                 (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
 109
 110 #define CONFIG_SYS_DDR_INTERVAL ((0x800 << SDRAM_INTERVAL_REFINT_SHIFT) |\
 111                                 (0x800 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 112
 113 #define CONFIG_SYS_SDRAM_CFG            (SDRAM_CFG_SREN |\
 114                                          SDRAM_CFG_2T_EN | SDRAM_CFG_HSE |\
 115                                          SDRAM_CFG_DBW_32 |\
 116                                          SDRAM_CFG_SDRAM_TYPE_DDR2)
 117
 118 #define CONFIG_SYS_SDRAM_CFG2           0x00401000
 119 #define CONFIG_SYS_DDR_MODE             ((0x0448 << SDRAM_MODE_ESD_SHIFT) |\
 120                                          (0x0242 << SDRAM_MODE_SD_SHIFT))
 121 #define CONFIG_SYS_DDR_MODE_2           0x00000000
 122 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075
 123 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN |\
 124                                          DDRCDR_PZ_NOMZ |\
 125                                          DDRCDR_NZ_NOMZ |\
 126                                          DDRCDR_ODT |\
 127                                          DDRCDR_M_ODR |\
 128                                          DDRCDR_Q_DRN)
 129
 130 /*
 131  * on-board devices
 132  */
 133 #define CONFIG_TSEC1
 134 #define CONFIG_TSEC2
 135
 136 /*
 137  * NOR FLASH setup
 138  */
 139 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_8BIT
 140 #define CONFIG_FLASH_SHOW_PROGRESS      50
 141
 142 #define CONFIG_SYS_FLASH_BASE           0xFF800000
 143 #define CONFIG_SYS_FLASH_SIZE           8
 144
 145
 146 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 147 #define CONFIG_SYS_MAX_FLASH_SECT       128
 148
 149 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000
 150 #define CONFIG_SYS_FLASH_WRITE_TOUT     500
 151
 152 /*
 153  * NAND FLASH setup
 154  */
 155 #define CONFIG_SYS_NAND_BASE            0xE1000000
 156 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 157 #define CONFIG_SYS_NAND_MAX_CHIPS       1
 158 #define CONFIG_NAND_FSL_ELBC
 159 #define CONFIG_SYS_NAND_PAGE_SIZE       (2048)
 160 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 << 10)
 161 #define NAND_CACHE_PAGES                64
 162
 163
 164 /*
 165  * MRAM setup
 166  */
 167 #define CONFIG_SYS_MRAM_BASE            0xE2000000
 168 #define CONFIG_SYS_MRAM_SIZE            0x20000 /* 128 Kb */
 169
 170 #define CONFIG_SYS_OR_TIMING_MRAM
 171
 172
 173 /*
 174  * CPLD setup
 175  */
 176 #define CONFIG_SYS_CPLD_BASE            0xE3000000
 177 #define CONFIG_SYS_CPLD_SIZE            0x8000
 178
 179 #define CONFIG_SYS_OR_TIMING_MRAM
 180
 181
 182 /*
 183  * HW-Watchdog
 184  */
 185 #define CONFIG_WATCHDOG         1
 186 #define CONFIG_SYS_WATCHDOG_VALUE       0xFFFF
 187
 188 /*
 189  * I2C setup
 190  */
 191 #define CONFIG_SYS_I2C
 192 #define CONFIG_SYS_I2C_FSL
 193 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 194 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 195 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3100
 196 #define CONFIG_RTC_PCF8563
 197 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
 198
 199 /*
 200  * Ethernet setup
 201  */
 202 #ifdef CONFIG_TSEC1
 203 #define CONFIG_HAS_ETH0
 204 #define CONFIG_TSEC1_NAME               "TSEC0"
 205 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 206 #define TSEC1_PHY_ADDR                  0x1
 207 #define TSEC1_FLAGS                     TSEC_GIGABIT
 208 #define TSEC1_PHYIDX                    0
 209 #endif
 210
 211 #ifdef CONFIG_TSEC2
 212 #define CONFIG_HAS_ETH1
 213 #define CONFIG_TSEC2_NAME               "TSEC1"
 214 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 215 #define TSEC2_PHY_ADDR                  0x3
 216 #define TSEC2_FLAGS                     TSEC_GIGABIT
 217 #define TSEC2_PHYIDX                    0
 218 #endif
 219 #define CONFIG_ETHPRIME         "TSEC1"
 220
 221 /*
 222  * Serial Port
 223  */
 224 #define CONFIG_SYS_NS16550_SERIAL
 225 #define CONFIG_SYS_NS16550_REG_SIZE     1
 226
 227 #define CONFIG_SYS_BAUDRATE_TABLE       \
 228         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 229 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
 230 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
 231 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0))
 232
 233 #define CONFIG_HAS_FSL_DR_USB
 234 #define CONFIG_SYS_SCCR_USBDRCM 3
 235
 236 /*
 237  * U-Boot environment setup
 238  */
 239 #define CONFIG_BOOTP_BOOTFILESIZE
 240
 241 /*
 242  * The reserved memory
 243  */
 244 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 245 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 246 #define CONFIG_SYS_MALLOC_LEN           (8 * 1024 * 1024)
 247
 248 /*
 249  * Environment Configuration
 250  */
 251 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE \
 252                                 + CONFIG_SYS_MONITOR_LEN)
 253 #define CONFIG_ENV_SIZE         0x20000
 254 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
 255 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 256
 257 #define CONFIG_NETDEV                   eth1
 258 #define CONFIG_HOSTNAME         "ids8313"
 259 #define CONFIG_ROOTPATH         "/opt/eldk-4.2/ppc_6xx"
 260 #define CONFIG_BOOTFILE         "ids8313/uImage"
 261 #define CONFIG_UBOOTPATH                "ids8313/u-boot.bin"
 262 #define CONFIG_FDTFILE                  "ids8313/ids8313.dtb"
 263 #define CONFIG_LOADADDR         0x400000
 264 #define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mo,eth1addr:mo"
 265
 266 /* Initial Memory map for Linux*/
 267 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 268
 269 /*
 270  * Miscellaneous configurable options
 271  */
 272 #define CONFIG_SYS_CBSIZE               1024
 273 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 274
 275 #define CONFIG_SYS_MEMTEST_START        0x00001000
 276 #define CONFIG_SYS_MEMTEST_END          0x00C00000
 277
 278 #define CONFIG_SYS_LOAD_ADDR            0x100000
 279 #define CONFIG_LOADS_ECHO
 280 #define CONFIG_TIMESTAMP
 281 #define CONFIG_PREBOOT                  "echo;" \
 282                                         "echo Type \\\"run nfsboot\\\" " \
 283                                         "to mount root filesystem over NFS;echo"
 284 #define CONFIG_BOOTCOMMAND              "run boot_cramfs"
 285 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE
 286
 287 #define CONFIG_JFFS2_NAND
 288 #define CONFIG_JFFS2_DEV                "0"
 289
 290 /* mtdparts command line support */
 291
 292 #define CONFIG_EXTRA_ENV_SETTINGS \
 293         "netdev=" __stringify(CONFIG_NETDEV) "\0"                       \
 294         "ethprime=TSEC1\0"                                              \
 295         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 296         "tftpflash=tftpboot ${loadaddr} ${uboot}; "                     \
 297                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 298                 " +${filesize}; "                                       \
 299                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 300                 " +${filesize}; "                                       \
 301                 "cp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE)   \
 302                 " ${filesize}; "                                        \
 303                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 304                 " +${filesize}; "                                       \
 305                 "cmp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE)  \
 306                 " ${filesize}\0"                                        \
 307         "console=ttyS0\0"                                               \
 308         "fdtaddr=0x780000\0"                                            \
 309         "kernel_addr=ff800000\0"                                        \
 310         "fdtfile=" __stringify(CONFIG_FDTFILE) "\0"                     \
 311         "setbootargs=setenv bootargs "                                  \
 312                 "root=${rootdev} rw console=${console},"                \
 313                         "${baudrate} ${othbootargs}\0"                  \
 314         "setipargs=setenv bootargs root=${rootdev} rw "                 \
 315                         "nfsroot=${serverip}:${rootpath} "              \
 316                         "ip=${ipaddr}:${serverip}:${gatewayip}:"        \
 317                         "${netmask}:${hostname}:${netdev}:off "         \
 318                         "console=${console},${baudrate} ${othbootargs}\0" \
 319         "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"              \
 320         "mtdids=" CONFIG_MTDIDS_DEFAULT "\0"                                    \
 321         "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"                                \
 322         "\0"
 323
 324 #define CONFIG_NFSBOOTCOMMAND                                           \
 325         "setenv rootdev /dev/nfs;"                                      \
 326         "run setipargs;run addmtd;"                                     \
 327         "tftp ${loadaddr} ${bootfile};"                         \
 328         "tftp ${fdtaddr} ${fdtfile};"                                   \
 329         "fdt addr ${fdtaddr};"                                          \
 330         "bootm ${loadaddr} - ${fdtaddr}"
 331
 332 /* UBI Support */
 333
 334 #endif  /* __CONFIG_H */