1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
7 * Copyright (c) 2011 IDS GmbH, Germany
8 * Sergej Stepanov <ste@ids.de>
15 * High Level Configuration Options
17 #define CONFIG_FSL_ELBC
19 #define CONFIG_BOOT_RETRY_TIME 900
20 #define CONFIG_BOOT_RETRY_MIN 30
21 #define CONFIG_RESET_TO_RETRY
23 #define CONFIG_SYS_SICRH 0x00000000
24 #define CONFIG_SYS_SICRL (SICRL_LBC | SICRL_SPI_D)
26 #define CONFIG_HWCONFIG
29 * Definitions for initial stack pointer and data area (in DCACHE )
31 #define CONFIG_SYS_INIT_RAM_LOCK
32 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000
33 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in DPRAM */
34 #define CONFIG_SYS_GBL_DATA_SIZE 0x100
35 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
36 - CONFIG_SYS_GBL_DATA_SIZE)
37 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
40 * Local Bus LCRR and LBCR regs
42 #define CONFIG_SYS_LBC_LBCR (0x00040000 |\
43 (0xFF << LBCR_BMT_SHIFT) |\
46 #define CONFIG_SYS_LBC_MRTPR 0x20000000
49 * Internal Definitions
54 #define CONFIG_SYS_DDR_BASE 0x00000000
55 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
56 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
59 * Manually set up DDR parameters,
60 * as this board has not the SPD connected to I2C.
62 #define CONFIG_SYS_DDR_SIZE 256 /* MB */
63 #define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN |\
65 CSCONFIG_ROW_BIT_13 |\
68 #define CONFIG_SYS_DDR_CONFIG_256 (CONFIG_SYS_DDR_CONFIG | \
71 #define CONFIG_SYS_DDR_TIMING_3 (1 << 16) /* ext refrec */
72 #define CONFIG_SYS_DDR_TIMING_0 ((3 << TIMING_CFG0_RWT_SHIFT) |\
73 (3 << TIMING_CFG0_WRT_SHIFT) |\
74 (3 << TIMING_CFG0_RRT_SHIFT) |\
75 (3 << TIMING_CFG0_WWT_SHIFT) |\
76 (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) |\
77 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) |\
78 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
79 (2 << TIMING_CFG0_MRS_CYC_SHIFT))
80 #define CONFIG_SYS_DDR_TIMING_1 ((4 << TIMING_CFG1_PRETOACT_SHIFT) |\
81 (12 << TIMING_CFG1_ACTTOPRE_SHIFT) |\
82 (4 << TIMING_CFG1_ACTTORW_SHIFT) |\
83 (7 << TIMING_CFG1_CASLAT_SHIFT) |\
84 (4 << TIMING_CFG1_REFREC_SHIFT) |\
85 (4 << TIMING_CFG1_WRREC_SHIFT) |\
86 (2 << TIMING_CFG1_ACTTOACT_SHIFT) |\
87 (2 << TIMING_CFG1_WRTORD_SHIFT))
88 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) |\
89 (5 << TIMING_CFG2_CPO_SHIFT) |\
90 (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) |\
91 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) |\
92 (0 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) |\
93 (1 << TIMING_CFG2_CKE_PLS_SHIFT) |\
94 (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
96 #define CONFIG_SYS_DDR_INTERVAL ((0x800 << SDRAM_INTERVAL_REFINT_SHIFT) |\
97 (0x800 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
99 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN |\
100 SDRAM_CFG_2T_EN | SDRAM_CFG_HSE |\
102 SDRAM_CFG_SDRAM_TYPE_DDR2)
104 #define CONFIG_SYS_SDRAM_CFG2 0x00401000
105 #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) |\
106 (0x0242 << SDRAM_MODE_SD_SHIFT))
107 #define CONFIG_SYS_DDR_MODE_2 0x00000000
108 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075
109 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN |\
125 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
126 #define CONFIG_FLASH_SHOW_PROGRESS 50
128 #define CONFIG_SYS_FLASH_BASE 0xFF800000
129 #define CONFIG_SYS_FLASH_SIZE 8
132 #define CONFIG_SYS_MAX_FLASH_BANKS 1
133 #define CONFIG_SYS_MAX_FLASH_SECT 128
135 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000
136 #define CONFIG_SYS_FLASH_WRITE_TOUT 500
141 #define CONFIG_SYS_NAND_BASE 0xE1000000
142 #define CONFIG_SYS_MAX_NAND_DEVICE 1
143 #define CONFIG_SYS_NAND_MAX_CHIPS 1
144 #define CONFIG_NAND_FSL_ELBC
145 #define CONFIG_SYS_NAND_PAGE_SIZE (2048)
146 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
147 #define NAND_CACHE_PAGES 64
153 #define CONFIG_SYS_MRAM_BASE 0xE2000000
154 #define CONFIG_SYS_MRAM_SIZE 0x20000 /* 128 Kb */
156 #define CONFIG_SYS_OR_TIMING_MRAM
162 #define CONFIG_SYS_CPLD_BASE 0xE3000000
163 #define CONFIG_SYS_CPLD_SIZE 0x8000
165 #define CONFIG_SYS_OR_TIMING_MRAM
171 #define CONFIG_WATCHDOG 1
172 #define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
177 #define CONFIG_SYS_I2C
178 #define CONFIG_SYS_I2C_FSL
179 #define CONFIG_SYS_FSL_I2C_SPEED 400000
180 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
181 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
182 #define CONFIG_RTC_PCF8563
183 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
189 #define CONFIG_HAS_ETH0
190 #define CONFIG_TSEC1_NAME "TSEC0"
191 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
192 #define TSEC1_PHY_ADDR 0x1
193 #define TSEC1_FLAGS TSEC_GIGABIT
194 #define TSEC1_PHYIDX 0
198 #define CONFIG_HAS_ETH1
199 #define CONFIG_TSEC2_NAME "TSEC1"
200 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
201 #define TSEC2_PHY_ADDR 0x3
202 #define TSEC2_FLAGS TSEC_GIGABIT
203 #define TSEC2_PHYIDX 0
205 #define CONFIG_ETHPRIME "TSEC1"
210 #define CONFIG_SYS_NS16550_SERIAL
211 #define CONFIG_SYS_NS16550_REG_SIZE 1
213 #define CONFIG_SYS_BAUDRATE_TABLE \
214 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
215 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
216 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
217 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
219 #define CONFIG_HAS_FSL_DR_USB
220 #define CONFIG_SYS_SCCR_USBDRCM 3
223 * U-Boot environment setup
225 #define CONFIG_BOOTP_BOOTFILESIZE
228 * The reserved memory
230 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
231 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
232 #define CONFIG_SYS_MALLOC_LEN (8 * 1024 * 1024)
235 * Environment Configuration
237 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \
238 + CONFIG_SYS_MONITOR_LEN)
239 #define CONFIG_ENV_SIZE 0x20000
240 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
241 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
243 #define CONFIG_NETDEV eth1
244 #define CONFIG_HOSTNAME "ids8313"
245 #define CONFIG_ROOTPATH "/opt/eldk-4.2/ppc_6xx"
246 #define CONFIG_BOOTFILE "ids8313/uImage"
247 #define CONFIG_UBOOTPATH "ids8313/u-boot.bin"
248 #define CONFIG_FDTFILE "ids8313/ids8313.dtb"
249 #define CONFIG_LOADADDR 0x400000
250 #define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mo,eth1addr:mo"
252 /* Initial Memory map for Linux*/
253 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
256 * Miscellaneous configurable options
258 #define CONFIG_SYS_CBSIZE 1024
259 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
261 #define CONFIG_SYS_MEMTEST_START 0x00001000
262 #define CONFIG_SYS_MEMTEST_END 0x00C00000
264 #define CONFIG_SYS_LOAD_ADDR 0x100000
265 #define CONFIG_LOADS_ECHO
266 #define CONFIG_TIMESTAMP
267 #define CONFIG_PREBOOT "echo;" \
268 "echo Type \\\"run nfsboot\\\" " \
269 "to mount root filesystem over NFS;echo"
270 #define CONFIG_BOOTCOMMAND "run boot_cramfs"
271 #undef CONFIG_SYS_LOADS_BAUD_CHANGE
273 #define CONFIG_JFFS2_NAND
274 #define CONFIG_JFFS2_DEV "0"
276 /* mtdparts command line support */
278 #define CONFIG_EXTRA_ENV_SETTINGS \
279 "netdev=" __stringify(CONFIG_NETDEV) "\0" \
281 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
282 "tftpflash=tftpboot ${loadaddr} ${uboot}; " \
283 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
285 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
287 "cp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \
289 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
291 "cmp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \
294 "fdtaddr=0x780000\0" \
295 "kernel_addr=ff800000\0" \
296 "fdtfile=" __stringify(CONFIG_FDTFILE) "\0" \
297 "setbootargs=setenv bootargs " \
298 "root=${rootdev} rw console=${console}," \
299 "${baudrate} ${othbootargs}\0" \
300 "setipargs=setenv bootargs root=${rootdev} rw " \
301 "nfsroot=${serverip}:${rootpath} " \
302 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
303 "${netmask}:${hostname}:${netdev}:off " \
304 "console=${console},${baudrate} ${othbootargs}\0" \
305 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
306 "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
307 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
310 #define CONFIG_NFSBOOTCOMMAND \
311 "setenv rootdev /dev/nfs;" \
312 "run setipargs;run addmtd;" \
313 "tftp ${loadaddr} ${bootfile};" \
314 "tftp ${fdtaddr} ${fdtfile};" \
315 "fdt addr ${fdtaddr};" \
316 "bootm ${loadaddr} - ${fdtaddr}"
320 #endif /* __CONFIG_H */