3 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * Config header file for Hymod board
32 * High Level Configuration Options
36 #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
37 #define CONFIG_HYMOD 1 /* ...on a Hymod board */
39 #define CONFIG_BOARD_POSTCLK_INIT /* have board_postclk_init() function */
42 * select serial console configuration
44 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
45 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
48 * if CONFIG_CONS_NONE is defined, then the serial console routines must
49 * defined elsewhere (for example, on the cogent platform, there are serial
50 * ports on the motherboard which are used for the serial console - see
51 * cogent/cma101/serial.[ch]).
53 #undef CONFIG_CONS_ON_SMC /* define if console on SMC */
54 #define CONFIG_CONS_ON_SCC /* define if console on SCC */
55 #undef CONFIG_CONS_NONE /* define if console on something else*/
56 #define CONFIG_CONS_INDEX 1 /* which serial channel for console */
57 #define CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */
58 #define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */
59 #define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
62 * select ethernet configuration
64 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
65 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
68 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
69 * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
70 * from CONFIG_COMMANDS to remove support for networking.
72 #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
73 #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
74 #undef CONFIG_ETHER_NONE /* define if ether on something else */
75 #define CONFIG_ETHER_INDEX 1 /* which channel for ether */
77 #if (CONFIG_ETHER_INDEX == 1)
82 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
83 * - Enable Full Duplex in FSMR
85 # define CFG_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
86 # define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK11)
87 # define CFG_CPMFCR_RAMTYPE 0
88 # define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
90 #elif (CONFIG_ETHER_INDEX == 2)
95 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
96 * - Enable Full Duplex in FSMR
98 # define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
99 # define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
100 # define CFG_CPMFCR_RAMTYPE 0
101 # define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
103 #elif (CONFIG_ETHER_INDEX == 3)
108 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
109 * - Enable Full Duplex in FSMR
111 # define CFG_CMXFCR_MASK (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
112 # define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
113 # define CFG_CPMFCR_RAMTYPE 0
114 # define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
116 #endif /* CONFIG_ETHER_INDEX */
120 #define CONFIG_HARD_I2C 1 /* To enable I2C hardware support */
122 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
124 #define CONFIG_8260_CLKIN 33333333 /* in Hz */
126 #define CONFIG_8260_CLKIN 66666666 /* in Hz */
129 #if defined(CONFIG_CONS_USE_EXTC)
130 #define CONFIG_BAUDRATE 115200
132 #define CONFIG_BAUDRATE 38400
135 /* default ip addresses - these will be overridden */
136 #define CONFIG_IPADDR 192.168.1.1 /* hymod "boot" address */
137 #define CONFIG_SERVERIP 192.168.1.254 /* hymod "server" address */
139 #define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \
160 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
161 #include <cmd_confdefs.h>
164 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
167 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
168 #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
169 #define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
170 #undef CONFIG_KGDB_NONE /* define if kgdb on something else */
171 #define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
172 #define CONFIG_KGDB_USE_EXTC /* SMC/SCC use ext clock not brg_clk */
173 #define CONFIG_KGDB_EXTC_RATE 3686400 /* serial ext clk rate in Hz */
174 #define CONFIG_KGDB_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
175 # if defined(CONFIG_KGDB_USE_EXTC)
176 #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
178 #define CONFIG_KGDB_BAUDRATE 38400 /* speed to run kgdb serial port at */
182 #undef CONFIG_WATCHDOG /* disable platform specific watchdog */
184 #define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */
187 * Hymod specific configurable options
189 #undef CFG_HYMOD_DBLEDS /* walk mezz board LEDs */
192 * Miscellaneous configurable options
194 #define CFG_LONGHELP /* undef to save memory */
195 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
196 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
197 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
199 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
201 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
202 #define CFG_MAXARGS 16 /* max number of command args */
203 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
205 #define CFG_MEMTEST_START 0x00400000 /* memtest works on */
206 #define CFG_MEMTEST_END 0x03c00000 /* 4 ... 60 MB in DRAM */
208 #define CFG_LOAD_ADDR 0x100000 /* default load address */
210 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
212 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
214 #define CFG_I2C_SPEED 50000
215 #define CFG_I2C_SLAVE 0x7e
217 /* these are for the ST M24C02 2kbit serial i2c eeprom */
218 #define CFG_I2C_EEPROM_ADDR 0x50 /* base address */
219 #define CFG_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
220 #define CFG_I2C_RTC_ADDR 0x51 /* philips PCF8563 RTC address */
223 * Low Level Configuration Settings
224 * (address mappings, register initial values, etc.)
225 * You should know what you are doing if you make changes here.
228 /*-----------------------------------------------------------------------
229 * Hard Reset Configuration Words
231 * if you change bits in the HRCW, you must also change the CFG_*
232 * defines for the various registers affected by the HRCW e.g. changing
233 * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
236 #define CFG_HRCW_MASTER (HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\
237 HRCW_ISB100|HRCW_BMS|HRCW_MMR11|HRCW_APPC10|\
240 #define CFG_HRCW_MASTER (HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\
241 HRCW_ISB100|HRCW_BMS|HRCW_MMR11|HRCW_APPC10|\
244 /* no slaves so just duplicate the master hrcw */
245 #define CFG_HRCW_SLAVE1 CFG_HRCW_MASTER
246 #define CFG_HRCW_SLAVE2 CFG_HRCW_MASTER
247 #define CFG_HRCW_SLAVE3 CFG_HRCW_MASTER
248 #define CFG_HRCW_SLAVE4 CFG_HRCW_MASTER
249 #define CFG_HRCW_SLAVE5 CFG_HRCW_MASTER
250 #define CFG_HRCW_SLAVE6 CFG_HRCW_MASTER
251 #define CFG_HRCW_SLAVE7 CFG_HRCW_MASTER
253 /*-----------------------------------------------------------------------
254 * Internal Memory Mapped Register
256 #define CFG_IMMR 0xF0000000
258 /*-----------------------------------------------------------------------
259 * Definitions for initial stack pointer and data area (in DPRAM)
261 #define CFG_INIT_RAM_ADDR CFG_IMMR
262 #define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
263 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
264 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
265 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
267 /*-----------------------------------------------------------------------
268 * Start addresses for the final memory configuration
269 * (Set up by the startup code)
270 * Please note that CFG_SDRAM_BASE _must_ start at 0
272 #define CFG_SDRAM_BASE 0x00000000
273 #define CFG_FLASH_BASE TEXT_BASE
274 #define CFG_MONITOR_BASE TEXT_BASE
275 #define CFG_FPGA_BASE 0x80000000
277 * unfortunately, CFG_MONITOR_LEN must include the
278 * (very large i.e. 256kB) environment flash sector
280 #define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor*/
281 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
284 * For booting Linux, the board info and command line data
285 * have to be in the first 8 MB of memory, since this is
286 * the maximum mapped by the Linux kernel during initialization.
288 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/
290 /*-----------------------------------------------------------------------
293 #define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks */
294 #define CFG_MAX_FLASH_SECT 67 /* max num of sects on one chip */
296 #define CFG_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (in ms) */
297 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
299 #define CFG_FLASH_TYPE FLASH_28F640J3A
300 #define CFG_FLASH_ID (INTEL_ID_28F640J3A & 0xff)
301 #define CFG_FLASH_NBLOCKS 64
303 #define CFG_ENV_IS_IN_FLASH 1
304 #define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
305 #define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sect real size */
306 #define CFG_ENV_ADDR (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE)
308 /*-----------------------------------------------------------------------
309 * Cache Configuration
311 #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
312 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
313 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value*/
316 /*-----------------------------------------------------------------------
317 * HIDx - Hardware Implementation-dependent Registers 2-11
318 *-----------------------------------------------------------------------
319 * HID0 also contains cache control - initially enable both caches and
320 * invalidate contents, then the final state leaves only the instruction
321 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
322 * but Soft reset does not.
324 * HID1 has only read-only information - nothing to set.
326 #define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
329 #define CFG_HID0_FINAL 0
331 #define CFG_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE)
335 /*-----------------------------------------------------------------------
336 * RMR - Reset Mode Register 5-5
337 *-----------------------------------------------------------------------
338 * turn on Checkstop Reset Enable
343 #define CFG_RMR RMR_CSRE
346 /*-----------------------------------------------------------------------
347 * BCR - Bus Configuration 4-25
348 *-----------------------------------------------------------------------
350 #define CFG_BCR (BCR_ETM)
352 /*-----------------------------------------------------------------------
353 * SIUMCR - SIU Module Configuration 4-31
354 *-----------------------------------------------------------------------
356 #define CFG_SIUMCR (SIUMCR_DPPC10|SIUMCR_L2CPC01|\
357 SIUMCR_APPC10|SIUMCR_MMR11)
359 /*-----------------------------------------------------------------------
360 * SYPCR - System Protection Control 4-35
361 * SYPCR can only be written once after reset!
362 *-----------------------------------------------------------------------
363 * Watchdog & Bus Monitor Timer max, 60x & Local Bus Monitor enable
365 #if defined(CONFIG_WATCHDOG)
366 #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
367 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
369 #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
370 SYPCR_SWRI|SYPCR_SWP)
371 #endif /* CONFIG_WATCHDOG */
373 /*-----------------------------------------------------------------------
374 * TMCNTSC - Time Counter Status and Control 4-40
375 *-----------------------------------------------------------------------
376 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
377 * and enable Time Counter
379 #define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
381 /*-----------------------------------------------------------------------
382 * PISCR - Periodic Interrupt Status and Control 4-42
383 *-----------------------------------------------------------------------
384 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
387 #define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
389 /*-----------------------------------------------------------------------
390 * SCCR - System Clock Control 9-8
391 *-----------------------------------------------------------------------
392 * Ensure DFBRG is Divide by 16
394 #define CFG_SCCR (SCCR_DFBRG01)
396 /*-----------------------------------------------------------------------
397 * RCCR - RISC Controller Configuration 13-7
398 *-----------------------------------------------------------------------
403 * Init Memory Controller:
405 * Bank Bus Machine PortSz Device
406 * ---- --- ------- ------ ------
407 * 0 60x GPCM 32 bit FLASH
408 * 1 60x GPCM 32 bit FLASH (same as 0 - unused for now)
409 * 2 60x SDRAM 64 bit SDRAM
410 * 3 Local UPMC 8 bit Main Xilinx configuration
411 * 4 Local GPCM 32 bit Main Xilinx register mode
412 * 5 Local UPMB 32 bit Main Xilinx port mode
413 * 6 Local UPMC 8 bit Mezz Xilinx configuration
419 * Quotes from the HYMOD IO Board Reference manual:
421 * "The flash memory is two Intel StrataFlash chips, each configured for
422 * 16 bit operation and connected to give a 32 bit wide port."
424 * "The chip select logic is configured to respond to both *CS0 and *CS1.
425 * Therefore the FLASH memory will be mapped to both bank 0 and bank 1.
426 * It is suggested that bank 0 be read-only and bank 1 be read/write. The
427 * FLASH will then appear as ROM during boot."
429 * Initially, we are only going to use bank 0 in read/write mode.
432 /* 32 bit, read-write, GPCM on 60x bus */
433 #define CFG_BR0_PRELIM ((CFG_FLASH_BASE&BRx_BA_MSK)|\
434 BRx_PS_32|BRx_MS_GPCM_P|BRx_V)
436 #define CFG_OR0_PRELIM (MEG_TO_AM(32)|ORxG_CSNT|ORxG_ACS_DIV2|ORxG_SCY_10_CLK)
441 * Quotes from the HYMOD IO Board Reference manual:
443 * "The main memory is implemented using TC59SM716FTL-10 SDRAM and has a
444 * fixed size of 64 Mbytes. The Toshiba TC59SM716FTL-10 is a CMOS synchronous
445 * dynamic random access memory organised as 4 banks by 4096 rows by 512
446 * columns by 16 bits. Four chips provide a 64-bit port on the 60x bus."
448 * "The locations in SDRAM are accessed using multiplexed address pins to
449 * specify row and column. The pins also act to specify commands. The state
450 * of the inputs *RAS, *CAS and *WE defines the required action. The a10/AP
451 * pin may function as a row address or as the AUTO PRECHARGE control line,
452 * depending on the cycle type. The 60x bus SDRAM machine allows the MPC8260
453 * address lines to be configured to the required multiplexing scheme."
456 #define CFG_SDRAM_SIZE 64
458 /* 64 bit, read-write, SDRAM on 60x bus */
459 #define CFG_BR2_PRELIM ((CFG_SDRAM_BASE&BRx_BA_MSK)|\
460 BRx_PS_64|BRx_MS_SDRAM_P|BRx_V)
461 /* 64 Mb, 4 int banks per dev, row start addr bit = A6, 12 row addr lines */
462 #define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM_SIZE)|\
463 ORxS_BPD_4|ORxS_ROWST_PBI1_A6|ORxS_NUMR_12)
466 * The 60x Bus SDRAM Mode Register (PDSMR) is set as follows:
468 * Page Based Interleaving, Refresh Enable, Address Multiplexing where A5
469 * is output on A16 pin (A6 on A17, and so on), use address pins A14-A16
470 * as bank select, A7 is output on SDA10 during an ACTIVATE command,
471 * earliest timing for ACTIVATE command after REFRESH command is 6 clocks,
472 * earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
473 * is 2 clocks, earliest timing for READ/WRITE command after ACTIVATE
474 * command is 2 clocks, earliest timing for PRECHARGE after last data
475 * was read is 1 clock, earliest timing for PRECHARGE after last data
476 * was written is 1 clock, CAS Latency is 2.
479 #define CFG_PSDMR (PSDMR_PBI|PSDMR_SDAM_A16_IS_A5|\
480 PSDMR_BSMA_A14_A16|PSDMR_SDA10_PBI1_A7|\
481 PSDMR_RFRC_6_CLK|PSDMR_PRETOACT_2W|\
482 PSDMR_ACTTORW_2W|PSDMR_LDOTOPRE_1C|\
483 PSDMR_WRC_1C|PSDMR_CL_2)
486 * The 60x bus-assigned SDRAM Refresh Timer (PSRT) (10-31) and the Refresh
487 * Timers Prescale (PTP) value in the Memory Refresh Timer Prescaler Register
488 * (MPTPR) (10-32) must also be set up (it used to be called the Periodic Timer
489 * Prescaler, hence the P instead of the R). The refresh timer period is given
490 * by (note that there was a change in the 8260 UM Errata):
492 * TimerPeriod = (PSRT + 1) / Fmptc
494 * where Fmptc is the BusClock divided by PTP. i.e.
496 * TimerPeriod = (PSRT + 1) / (BusClock / PTP)
500 * TImerPeriod = (PTP * (PSRT + 1)) / BusClock
502 * The requirement for the Toshiba TC59SM716FTL-10 is that there must be
503 * 4K refresh cycles every 64 ms. i.e. one refresh cycle every 64000/4096
506 * So PTP * (PSRT + 1) <= 15.625 * BusClock. At 66.666MHz, PSRT=31 and PTP=32
507 * appear to be reasonable.
512 #define CFG_MPTPR MPTPR_PTP_DIV8
515 #define CFG_MPTPR MPTPR_PTP_DIV32
519 * Banks 3,4,5 and 6 - FPGA access
521 * Quotes from the HYMOD IO Board Reference manual:
523 * "The IO Board is fitted with a Xilinx XCV300E main FPGA. Provision is made
524 * for configuring an optional FPGA on the mezzanine interface.
526 * Access to the FPGAs may be divided into several catagories:
529 * 2. Register mode access
530 * 3. Port mode access
532 * The main FPGA is supported for modes 1, 2 and 3. The mezzanine FPGA can be
533 * configured only (mode 1). Consequently there are four access types.
535 * To improve interface performance and simplify software design, the four
536 * possible access types are separately mapped to different memory banks.
538 * All are accessed using the local bus."
540 * Device Mode Memory Bank Machine Port Size Access
542 * Main Configuration 3 UPMC 8bit R/W
543 * Main Register 4 GPCM 32bit R/W
544 * Main Port 5 UPMB 32bit R/W
545 * Mezzanine Configuration 6 UPMC 8bit W/O
547 * "Note that mezzanine mode 1 access is write-only."
550 /* all the bank sizes must be a power of two, greater or equal to 32768 */
551 #define FPGA_MAIN_CFG_BASE (CFG_FPGA_BASE)
552 #define FPGA_MAIN_CFG_SIZE 32768
553 #define FPGA_MAIN_REG_BASE (FPGA_MAIN_CFG_BASE + FPGA_MAIN_CFG_SIZE)
554 #define FPGA_MAIN_REG_SIZE 32768
555 #define FPGA_MAIN_PORT_BASE (FPGA_MAIN_REG_BASE + FPGA_MAIN_REG_SIZE)
556 #define FPGA_MAIN_PORT_SIZE 32768
557 #define FPGA_MEZZ_CFG_BASE (FPGA_MAIN_PORT_BASE + FPGA_MAIN_PORT_SIZE)
558 #define FPGA_MEZZ_CFG_SIZE 32768
560 /* 8 bit, read-write, UPMC */
561 #define CFG_BR3_PRELIM (FPGA_MAIN_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V)
562 /* up to 32Kbyte, burst inhibit */
563 #define CFG_OR3_PRELIM (P2SZ_TO_AM(FPGA_MAIN_CFG_SIZE)|ORxU_BI)
565 /* 32 bit, read-write, GPCM */
566 #define CFG_BR4_PRELIM (FPGA_MAIN_REG_BASE|BRx_PS_32|BRx_MS_GPCM_L|BRx_V)
568 #define CFG_OR4_PRELIM (P2SZ_TO_AM(FPGA_MAIN_REG_SIZE))
570 /* 32 bit, read-write, UPMB */
571 #define CFG_BR5_PRELIM (FPGA_MAIN_PORT_BASE|BRx_PS_32|BRx_MS_UPMB|BRx_V)
573 #define CFG_OR5_PRELIM (P2SZ_TO_AM(FPGA_MAIN_PORT_SIZE)|ORxU_BI)
575 /* 8 bit, write-only, UPMC */
576 #define CFG_BR6_PRELIM (FPGA_MEZZ_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V)
577 /* up to 32Kbyte, burst inhibit */
578 #define CFG_OR6_PRELIM (P2SZ_TO_AM(FPGA_MEZZ_CFG_SIZE)|ORxU_BI)
580 /*-----------------------------------------------------------------------
581 * MBMR - Machine B Mode 10-27
582 *-----------------------------------------------------------------------
584 #define CFG_MBMR (MxMR_BSEL|MxMR_OP_NORM) /* XXX - needs more */
586 /*-----------------------------------------------------------------------
587 * MCMR - Machine C Mode 10-27
588 *-----------------------------------------------------------------------
590 #define CFG_MCMR (MxMR_BSEL|MxMR_DSx_2_CYCL) /* XXX - needs more */
593 * FPGA I/O Port/Bit information
596 #define FPGA_MAIN_PROG_PORT IOPIN_PORTA
597 #define FPGA_MAIN_PROG_PIN 4 /* PA4 */
598 #define FPGA_MAIN_INIT_PORT IOPIN_PORTA
599 #define FPGA_MAIN_INIT_PIN 5 /* PA5 */
600 #define FPGA_MAIN_DONE_PORT IOPIN_PORTA
601 #define FPGA_MAIN_DONE_PIN 6 /* PA6 */
603 #define FPGA_MEZZ_PROG_PORT IOPIN_PORTA
604 #define FPGA_MEZZ_PROG_PIN 0 /* PA0 */
605 #define FPGA_MEZZ_INIT_PORT IOPIN_PORTA
606 #define FPGA_MEZZ_INIT_PIN 1 /* PA1 */
607 #define FPGA_MEZZ_DONE_PORT IOPIN_PORTA
608 #define FPGA_MEZZ_DONE_PIN 2 /* PA2 */
609 #define FPGA_MEZZ_ENABLE_PORT IOPIN_PORTA
610 #define FPGA_MEZZ_ENABLE_PIN 3 /* PA3 */
613 * Internal Definitions
617 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
618 #define BOOTFLAG_WARM 0x02 /* Software reboot */
620 #endif /* __CONFIG_H */