3 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * Config header file for Hymod board
32 * High Level Configuration Options
36 #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
37 #define CONFIG_HYMOD 1 /* ...on a Hymod board */
39 #define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
41 #define CONFIG_BOARD_POSTCLK_INIT /* have board_postclk_init() function */
44 * select serial console configuration
46 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
47 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
50 * if CONFIG_CONS_NONE is defined, then the serial console routines must
51 * defined elsewhere (for example, on the cogent platform, there are serial
52 * ports on the motherboard which are used for the serial console - see
53 * cogent/cma101/serial.[ch]).
55 #undef CONFIG_CONS_ON_SMC /* define if console on SMC */
56 #define CONFIG_CONS_ON_SCC /* define if console on SCC */
57 #undef CONFIG_CONS_NONE /* define if console on something else*/
58 #define CONFIG_CONS_INDEX 1 /* which serial channel for console */
59 #define CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */
60 #define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */
61 #define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
64 * select ethernet configuration
66 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
67 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
70 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
71 * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
72 * from CONFIG_COMMANDS to remove support for networking.
74 #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
75 #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
76 #undef CONFIG_ETHER_NONE /* define if ether on something else */
77 #define CONFIG_ETHER_INDEX 1 /* which channel for ether */
78 #define CONFIG_ETHER_LOOPBACK_TEST /* add ether external loopback test */
80 #ifdef CONFIG_ETHER_ON_FCC
82 #if (CONFIG_ETHER_INDEX == 1)
87 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
88 * - Enable Full Duplex in FSMR
90 # define CFG_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
91 # define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK11)
92 # define CFG_CPMFCR_RAMTYPE 0
93 # define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
95 # define MDIO_PORT 0 /* Port A */
96 # define MDIO_DATA_PINMASK 0x00040000 /* Pin 13 */
97 # define MDIO_CLCK_PINMASK 0x00080000 /* Pin 12 */
99 #elif (CONFIG_ETHER_INDEX == 2)
104 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
105 * - Enable Full Duplex in FSMR
107 # define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
108 # define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
109 # define CFG_CPMFCR_RAMTYPE 0
110 # define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
112 # define MDIO_PORT 0 /* Port A */
113 # define MDIO_DATA_PINMASK 0x00000040 /* Pin 25 */
114 # define MDIO_CLCK_PINMASK 0x00000080 /* Pin 24 */
116 #elif (CONFIG_ETHER_INDEX == 3)
121 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
122 * - Enable Full Duplex in FSMR
124 # define CFG_CMXFCR_MASK (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
125 # define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
126 # define CFG_CPMFCR_RAMTYPE 0
127 # define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
129 # define MDIO_PORT 0 /* Port A */
130 # define MDIO_DATA_PINMASK 0x00000100 /* Pin 23 */
131 # define MDIO_CLCK_PINMASK 0x00000200 /* Pin 22 */
133 #endif /* CONFIG_ETHER_INDEX */
135 #define CONFIG_MII /* MII PHY management */
136 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
138 #define MDIO_ACTIVE (iop->pdir |= MDIO_DATA_PINMASK)
139 #define MDIO_TRISTATE (iop->pdir &= ~MDIO_DATA_PINMASK)
140 #define MDIO_READ ((iop->pdat & MDIO_DATA_PINMASK) != 0)
142 #define MDIO(bit) if(bit) iop->pdat |= MDIO_DATA_PINMASK; \
143 else iop->pdat &= ~MDIO_DATA_PINMASK
145 #define MDC(bit) if(bit) iop->pdat |= MDIO_CLCK_PINMASK; \
146 else iop->pdat &= ~MDIO_CLCK_PINMASK
148 #define MIIDELAY udelay(1)
150 #endif /* CONFIG_ETHER_ON_FCC */
154 #define CONFIG_HARD_I2C 1 /* To enable I2C hardware support */
155 #define CONFIG_DTT_ADM1021 1 /* ADM1021 temp sensor support */
157 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
159 #define CONFIG_8260_CLKIN 33333333 /* in Hz */
161 #define CONFIG_8260_CLKIN 66666666 /* in Hz */
164 #if defined(CONFIG_CONS_USE_EXTC)
165 #define CONFIG_BAUDRATE 115200
167 #define CONFIG_BAUDRATE 9600
170 /* default ip addresses - these will be overridden */
171 #define CONFIG_IPADDR 192.168.1.1 /* hymod "boot" address */
172 #define CONFIG_SERVERIP 192.168.1.254 /* hymod "server" address */
174 #define CONFIG_LAST_STAGE_INIT
176 #define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \
199 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
200 #include <cmd_confdefs.h>
203 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
205 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
206 #define CONFIG_BOOT_RETRY_TIME 30 /* retry autoboot after 30 secs */
207 #define CONFIG_BOOT_RETRY_MIN 1 /* can go down to 1 second timeout */
208 /* Be selective on what keys can delay or stop the autoboot process
211 #define CONFIG_AUTOBOOT_KEYED
212 #define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, " \
213 "press <SPACE> to stop\n"
214 #define CONFIG_AUTOBOOT_STOP_STR " "
215 #undef CONFIG_AUTOBOOT_DELAY_STR
216 #define DEBUG_BOOTKEYS 0
219 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
220 #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
221 #define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
222 #undef CONFIG_KGDB_NONE /* define if kgdb on something else */
223 #define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
224 #define CONFIG_KGDB_USE_EXTC /* SMC/SCC use ext clock not brg_clk */
225 #define CONFIG_KGDB_EXTC_RATE 3686400 /* serial ext clk rate in Hz */
226 #define CONFIG_KGDB_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
227 # if defined(CONFIG_KGDB_USE_EXTC)
228 #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
230 #define CONFIG_KGDB_BAUDRATE 9600 /* speed to run kgdb serial port at */
234 #undef CONFIG_WATCHDOG /* disable platform specific watchdog */
236 #define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */
239 * Hymod specific configurable options
241 #undef CFG_HYMOD_DBLEDS /* walk mezz board LEDs */
244 * Miscellaneous configurable options
246 #define CFG_LONGHELP /* undef to save memory */
247 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
248 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
249 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
251 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
253 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
254 #define CFG_MAXARGS 16 /* max number of command args */
255 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
257 #define CFG_MEMTEST_START 0x00400000 /* memtest works on */
258 #define CFG_MEMTEST_END 0x03c00000 /* 4 ... 60 MB in DRAM */
260 #define CFG_CLKS_IN_HZ 1 /* everything, incl board info, in Hz */
262 #define CFG_LOAD_ADDR 0x100000 /* default load address */
264 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
266 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
268 #define CFG_I2C_SPEED 50000
269 #define CFG_I2C_SLAVE 0x7e
271 /* these are for the ST M24C02 2kbit serial i2c eeprom */
272 #define CFG_I2C_EEPROM_ADDR 0x50 /* base address */
273 #define CFG_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
274 /* mask of address bits that overflow into the "EEPROM chip address" */
275 #define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
277 #define CFG_EEPROM_PAGE_WRITE_ENABLE 1 /* write eeprom in pages */
278 #define CFG_EEPROM_PAGE_WRITE_BITS 4 /* 16 byte write page size */
279 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
281 #define CFG_I2C_MULTI_EEPROMS 1 /* hymod has two eeproms */
283 #define CFG_I2C_RTC_ADDR 0x51 /* philips PCF8563 RTC address */
286 * standard dtt sensor configuration - bottom bit will determine local or
287 * remote sensor of the ADM1021, the rest determines index into
288 * CFG_DTT_ADM1021 array below.
290 * On HYMOD board, the remote sensor should be connected to the MPC8260
291 * temperature diode thingy, but an errata said this didn't work and
292 * should be disabled - so it isn't connected.
295 #define CONFIG_DTT_SENSORS { 0, 1 }
297 #define CONFIG_DTT_SENSORS { 0 }
301 * ADM1021 temp sensor configuration (see dtt/adm1021.c for details).
302 * there will be one entry in this array for each two (dummy) sensors in
303 * CONFIG_DTT_SENSORS.
307 * - i2c addr 0x2a (both ADD0 and ADD1 are N/C)
308 * - conversion rate 0x02 = 0.25 conversions/second
309 * - ALERT ouput disabled
310 * - local temp sensor enabled, min set to 0 deg, max set to 85 deg
311 * - remote temp sensor disabled (see comment for CONFIG_DTT_SENSORS above)
313 #define CFG_DTT_ADM1021 { { 0x2a, 0x02, 0, 1, 0, 85, 0, } }
316 * Low Level Configuration Settings
317 * (address mappings, register initial values, etc.)
318 * You should know what you are doing if you make changes here.
321 /*-----------------------------------------------------------------------
322 * Hard Reset Configuration Words
324 * if you change bits in the HRCW, you must also change the CFG_*
325 * defines for the various registers affected by the HRCW e.g. changing
326 * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
329 #define CFG_HRCW_MASTER (HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\
330 HRCW_ISB100|HRCW_BMS|HRCW_MMR11|HRCW_APPC10|\
333 #define CFG_HRCW_MASTER (HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\
334 HRCW_ISB100|HRCW_BMS|HRCW_MMR11|HRCW_APPC10|\
337 /* no slaves so just duplicate the master hrcw */
338 #define CFG_HRCW_SLAVE1 CFG_HRCW_MASTER
339 #define CFG_HRCW_SLAVE2 CFG_HRCW_MASTER
340 #define CFG_HRCW_SLAVE3 CFG_HRCW_MASTER
341 #define CFG_HRCW_SLAVE4 CFG_HRCW_MASTER
342 #define CFG_HRCW_SLAVE5 CFG_HRCW_MASTER
343 #define CFG_HRCW_SLAVE6 CFG_HRCW_MASTER
344 #define CFG_HRCW_SLAVE7 CFG_HRCW_MASTER
346 /*-----------------------------------------------------------------------
347 * Internal Memory Mapped Register
349 #define CFG_IMMR 0xF0000000
351 /*-----------------------------------------------------------------------
352 * Definitions for initial stack pointer and data area (in DPRAM)
354 #define CFG_INIT_RAM_ADDR CFG_IMMR
355 #define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
356 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
357 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
358 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
360 /*-----------------------------------------------------------------------
361 * Start addresses for the final memory configuration
362 * (Set up by the startup code)
363 * Please note that CFG_SDRAM_BASE _must_ start at 0
365 #define CFG_SDRAM_BASE 0x00000000
366 #define CFG_FLASH_BASE TEXT_BASE
367 #define CFG_MONITOR_BASE TEXT_BASE
368 #define CFG_FPGA_BASE 0x80000000
370 * unfortunately, CFG_MONITOR_LEN must include the
371 * (very large i.e. 256kB) environment flash sector
373 #define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor*/
374 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
377 * For booting Linux, the board info and command line data
378 * have to be in the first 8 MB of memory, since this is
379 * the maximum mapped by the Linux kernel during initialization.
381 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/
383 /*-----------------------------------------------------------------------
386 #define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks */
387 #define CFG_MAX_FLASH_SECT 67 /* max num of sects on one chip */
389 #define CFG_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (in ms) */
390 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
392 #define CFG_ENV_IS_IN_FLASH 1
393 #define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
394 #define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sect real size */
395 #define CFG_ENV_ADDR (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE)
397 /*-----------------------------------------------------------------------
398 * Cache Configuration
400 #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
401 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
402 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value*/
405 /*-----------------------------------------------------------------------
406 * HIDx - Hardware Implementation-dependent Registers 2-11
407 *-----------------------------------------------------------------------
408 * HID0 also contains cache control - initially enable both caches and
409 * invalidate contents, then the final state leaves only the instruction
410 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
411 * but Soft reset does not.
413 * HID1 has only read-only information - nothing to set.
415 #define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
418 #define CFG_HID0_FINAL 0
420 #define CFG_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE)
424 /*-----------------------------------------------------------------------
425 * RMR - Reset Mode Register 5-5
426 *-----------------------------------------------------------------------
427 * turn on Checkstop Reset Enable
432 #define CFG_RMR RMR_CSRE
435 /*-----------------------------------------------------------------------
436 * BCR - Bus Configuration 4-25
437 *-----------------------------------------------------------------------
439 #define CFG_BCR (BCR_ETM)
441 /*-----------------------------------------------------------------------
442 * SIUMCR - SIU Module Configuration 4-31
443 *-----------------------------------------------------------------------
445 #define CFG_SIUMCR (SIUMCR_DPPC10|SIUMCR_L2CPC01|\
446 SIUMCR_APPC10|SIUMCR_MMR11)
448 /*-----------------------------------------------------------------------
449 * SYPCR - System Protection Control 4-35
450 * SYPCR can only be written once after reset!
451 *-----------------------------------------------------------------------
452 * Watchdog & Bus Monitor Timer max, 60x & Local Bus Monitor enable
454 #if defined(CONFIG_WATCHDOG)
455 #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
456 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
458 #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
459 SYPCR_SWRI|SYPCR_SWP)
460 #endif /* CONFIG_WATCHDOG */
462 /*-----------------------------------------------------------------------
463 * TMCNTSC - Time Counter Status and Control 4-40
464 *-----------------------------------------------------------------------
465 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
466 * and enable Time Counter
468 #define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
470 /*-----------------------------------------------------------------------
471 * PISCR - Periodic Interrupt Status and Control 4-42
472 *-----------------------------------------------------------------------
473 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
476 #define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
478 /*-----------------------------------------------------------------------
479 * SCCR - System Clock Control 9-8
480 *-----------------------------------------------------------------------
481 * Ensure DFBRG is Divide by 16
483 #define CFG_SCCR (SCCR_DFBRG01)
485 /*-----------------------------------------------------------------------
486 * RCCR - RISC Controller Configuration 13-7
487 *-----------------------------------------------------------------------
492 * Init Memory Controller:
494 * Bank Bus Machine PortSz Device
495 * ---- --- ------- ------ ------
496 * 0 60x GPCM 32 bit FLASH
497 * 1 60x GPCM 32 bit FLASH (same as 0 - unused for now)
498 * 2 60x SDRAM 64 bit SDRAM
499 * 3 Local UPMC 8 bit Main Xilinx configuration
500 * 4 Local GPCM 32 bit Main Xilinx register mode
501 * 5 Local UPMB 32 bit Main Xilinx port mode
502 * 6 Local UPMC 8 bit Mezz Xilinx configuration
508 * Quotes from the HYMOD IO Board Reference manual:
510 * "The flash memory is two Intel StrataFlash chips, each configured for
511 * 16 bit operation and connected to give a 32 bit wide port."
513 * "The chip select logic is configured to respond to both *CS0 and *CS1.
514 * Therefore the FLASH memory will be mapped to both bank 0 and bank 1.
515 * It is suggested that bank 0 be read-only and bank 1 be read/write. The
516 * FLASH will then appear as ROM during boot."
518 * Initially, we are only going to use bank 0 in read/write mode.
521 /* 32 bit, read-write, GPCM on 60x bus */
522 #define CFG_BR0_PRELIM ((CFG_FLASH_BASE&BRx_BA_MSK)|\
523 BRx_PS_32|BRx_MS_GPCM_P|BRx_V)
525 #define CFG_OR0_PRELIM (MEG_TO_AM(32)|ORxG_CSNT|ORxG_ACS_DIV2|ORxG_SCY_10_CLK)
530 * Quotes from the HYMOD IO Board Reference manual:
532 * "The main memory is implemented using TC59SM716FTL-10 SDRAM and has a
533 * fixed size of 64 Mbytes. The Toshiba TC59SM716FTL-10 is a CMOS synchronous
534 * dynamic random access memory organised as 4 banks by 4096 rows by 512
535 * columns by 16 bits. Four chips provide a 64-bit port on the 60x bus."
537 * "The locations in SDRAM are accessed using multiplexed address pins to
538 * specify row and column. The pins also act to specify commands. The state
539 * of the inputs *RAS, *CAS and *WE defines the required action. The a10/AP
540 * pin may function as a row address or as the AUTO PRECHARGE control line,
541 * depending on the cycle type. The 60x bus SDRAM machine allows the MPC8260
542 * address lines to be configured to the required multiplexing scheme."
545 #define CFG_SDRAM_SIZE 64
547 /* 64 bit, read-write, SDRAM on 60x bus */
548 #define CFG_BR2_PRELIM ((CFG_SDRAM_BASE&BRx_BA_MSK)|\
549 BRx_PS_64|BRx_MS_SDRAM_P|BRx_V)
550 /* 64 Mb, 4 int banks per dev, row start addr bit = A6, 12 row addr lines */
551 #define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM_SIZE)|\
552 ORxS_BPD_4|ORxS_ROWST_PBI1_A6|ORxS_NUMR_12)
555 * The 60x Bus SDRAM Mode Register (PDSMR) is set as follows:
557 * Page Based Interleaving, Refresh Enable, Address Multiplexing where A5
558 * is output on A16 pin (A6 on A17, and so on), use address pins A14-A16
559 * as bank select, A7 is output on SDA10 during an ACTIVATE command,
560 * earliest timing for ACTIVATE command after REFRESH command is 6 clocks,
561 * earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
562 * is 2 clocks, earliest timing for READ/WRITE command after ACTIVATE
563 * command is 2 clocks, earliest timing for PRECHARGE after last data
564 * was read is 1 clock, earliest timing for PRECHARGE after last data
565 * was written is 1 clock, CAS Latency is 2.
568 #define CFG_PSDMR (PSDMR_PBI|PSDMR_SDAM_A16_IS_A5|\
569 PSDMR_BSMA_A14_A16|PSDMR_SDA10_PBI1_A7|\
570 PSDMR_RFRC_6_CLK|PSDMR_PRETOACT_2W|\
571 PSDMR_ACTTORW_2W|PSDMR_LDOTOPRE_1C|\
572 PSDMR_WRC_1C|PSDMR_CL_2)
575 * The 60x bus-assigned SDRAM Refresh Timer (PSRT) (10-31) and the Refresh
576 * Timers Prescale (PTP) value in the Memory Refresh Timer Prescaler Register
577 * (MPTPR) (10-32) must also be set up (it used to be called the Periodic Timer
578 * Prescaler, hence the P instead of the R). The refresh timer period is given
579 * by (note that there was a change in the 8260 UM Errata):
581 * TimerPeriod = (PSRT + 1) / Fmptc
583 * where Fmptc is the BusClock divided by PTP. i.e.
585 * TimerPeriod = (PSRT + 1) / (BusClock / PTP)
589 * TImerPeriod = (PTP * (PSRT + 1)) / BusClock
591 * The requirement for the Toshiba TC59SM716FTL-10 is that there must be
592 * 4K refresh cycles every 64 ms. i.e. one refresh cycle every 64000/4096
595 * So PTP * (PSRT + 1) <= 15.625 * BusClock. At 66.666MHz, PSRT=31 and PTP=32
596 * appear to be reasonable.
601 #define CFG_MPTPR MPTPR_PTP_DIV8
604 #define CFG_MPTPR MPTPR_PTP_DIV32
608 * Banks 3,4,5 and 6 - FPGA access
610 * Quotes from the HYMOD IO Board Reference manual:
612 * "The IO Board is fitted with a Xilinx XCV300E main FPGA. Provision is made
613 * for configuring an optional FPGA on the mezzanine interface.
615 * Access to the FPGAs may be divided into several catagories:
618 * 2. Register mode access
619 * 3. Port mode access
621 * The main FPGA is supported for modes 1, 2 and 3. The mezzanine FPGA can be
622 * configured only (mode 1). Consequently there are four access types.
624 * To improve interface performance and simplify software design, the four
625 * possible access types are separately mapped to different memory banks.
627 * All are accessed using the local bus."
629 * Device Mode Memory Bank Machine Port Size Access
631 * Main Configuration 3 UPMC 8bit R/W
632 * Main Register 4 GPCM 32bit R/W
633 * Main Port 5 UPMB 32bit R/W
634 * Mezzanine Configuration 6 UPMC 8bit W/O
636 * "Note that mezzanine mode 1 access is write-only."
639 /* all the bank sizes must be a power of two, greater or equal to 32768 */
640 #define FPGA_MAIN_CFG_BASE (CFG_FPGA_BASE)
641 #define FPGA_MAIN_CFG_SIZE 32768
642 #define FPGA_MAIN_REG_BASE (FPGA_MAIN_CFG_BASE + FPGA_MAIN_CFG_SIZE)
643 #define FPGA_MAIN_REG_SIZE 32768
644 #define FPGA_MAIN_PORT_BASE (FPGA_MAIN_REG_BASE + FPGA_MAIN_REG_SIZE)
645 #define FPGA_MAIN_PORT_SIZE 32768
646 #define FPGA_MEZZ_CFG_BASE (FPGA_MAIN_PORT_BASE + FPGA_MAIN_PORT_SIZE)
647 #define FPGA_MEZZ_CFG_SIZE 32768
649 /* 8 bit, read-write, UPMC */
650 #define CFG_BR3_PRELIM (FPGA_MAIN_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V)
651 /* up to 32Kbyte, burst inhibit */
652 #define CFG_OR3_PRELIM (P2SZ_TO_AM(FPGA_MAIN_CFG_SIZE)|ORxU_BI)
654 /* 32 bit, read-write, GPCM */
655 #define CFG_BR4_PRELIM (FPGA_MAIN_REG_BASE|BRx_PS_32|BRx_MS_GPCM_L|BRx_V)
657 #define CFG_OR4_PRELIM (P2SZ_TO_AM(FPGA_MAIN_REG_SIZE))
659 /* 32 bit, read-write, UPMB */
660 #define CFG_BR5_PRELIM (FPGA_MAIN_PORT_BASE|BRx_PS_32|BRx_MS_UPMB|BRx_V)
662 #define CFG_OR5_PRELIM (P2SZ_TO_AM(FPGA_MAIN_PORT_SIZE)|ORxU_BI)
664 /* 8 bit, write-only, UPMC */
665 #define CFG_BR6_PRELIM (FPGA_MEZZ_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V)
666 /* up to 32Kbyte, burst inhibit */
667 #define CFG_OR6_PRELIM (P2SZ_TO_AM(FPGA_MEZZ_CFG_SIZE)|ORxU_BI)
669 /*-----------------------------------------------------------------------
670 * MBMR - Machine B Mode 10-27
671 *-----------------------------------------------------------------------
673 #define CFG_MBMR (MxMR_BSEL|MxMR_OP_NORM) /* XXX - needs more */
675 /*-----------------------------------------------------------------------
676 * MCMR - Machine C Mode 10-27
677 *-----------------------------------------------------------------------
679 #define CFG_MCMR (MxMR_BSEL|MxMR_DSx_2_CYCL) /* XXX - needs more */
682 * FPGA I/O Port/Bit information
685 #define FPGA_MAIN_PROG_PORT IOPIN_PORTA
686 #define FPGA_MAIN_PROG_PIN 4 /* PA4 */
687 #define FPGA_MAIN_INIT_PORT IOPIN_PORTA
688 #define FPGA_MAIN_INIT_PIN 5 /* PA5 */
689 #define FPGA_MAIN_DONE_PORT IOPIN_PORTA
690 #define FPGA_MAIN_DONE_PIN 6 /* PA6 */
692 #define FPGA_MEZZ_PROG_PORT IOPIN_PORTA
693 #define FPGA_MEZZ_PROG_PIN 0 /* PA0 */
694 #define FPGA_MEZZ_INIT_PORT IOPIN_PORTA
695 #define FPGA_MEZZ_INIT_PIN 1 /* PA1 */
696 #define FPGA_MEZZ_DONE_PORT IOPIN_PORTA
697 #define FPGA_MEZZ_DONE_PIN 2 /* PA2 */
698 #define FPGA_MEZZ_ENABLE_PORT IOPIN_PORTA
699 #define FPGA_MEZZ_ENABLE_PIN 3 /* PA3 */
702 * FPGA Interrupt configuration
704 #define FPGA_MAIN_IRQ SIU_INT_IRQ2
707 * Internal Definitions
711 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
712 #define BOOTFLAG_WARM 0x02 /* Software reboot */
714 #endif /* __CONFIG_H */