include/configs/hrcon.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2014
   4  * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
   5  *
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 /*
  12  * High Level Configuration Options
  13  */
  14 #define CONFIG_E300             1 /* E300 family */
  15
  16 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC83xx_ESDHC_ADDR
  17
  18 /*
  19  * System IO Config
  20  */
  21 #define CONFIG_SYS_SICRH (\
  22         SICRH_ESDHC_A_SD |\
  23         SICRH_ESDHC_B_SD |\
  24         SICRH_ESDHC_C_SD |\
  25         SICRH_GPIO_A_GPIO |\
  26         SICRH_GPIO_B_GPIO |\
  27         SICRH_IEEE1588_A_GPIO |\
  28         SICRH_USB |\
  29         SICRH_GTM_GPIO |\
  30         SICRH_IEEE1588_B_GPIO |\
  31         SICRH_ETSEC2_GPIO |\
  32         SICRH_GPIOSEL_1 |\
  33         SICRH_TMROBI_V3P3 |\
  34         SICRH_TSOBI1_V2P5 |\
  35         SICRH_TSOBI2_V2P5)      /* 0x0037f103 */
  36 #define CONFIG_SYS_SICRL (\
  37         SICRL_SPI_PF0 |\
  38         SICRL_UART_PF0 |\
  39         SICRL_IRQ_PF0 |\
  40         SICRL_I2C2_PF0 |\
  41         SICRL_ETSEC1_GTX_CLK125)        /* 0x00000000 */
  42
  43 /*
  44  * IMMR new address
  45  */
  46 #define CONFIG_SYS_IMMR         0xE0000000
  47
  48 /*
  49  * SERDES
  50  */
  51 #define CONFIG_FSL_SERDES
  52 #define CONFIG_FSL_SERDES1      0xe3000
  53
  54 /*
  55  * Arbiter Setup
  56  */
  57 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
  58 #define CONFIG_SYS_ACR_RPTCNT   3 /* Arbiter repeat count is 4 */
  59 #define CONFIG_SYS_SPCR_TSECEP  3 /* eTSEC emergency priority is highest */
  60
  61 /*
  62  * DDR Setup
  63  */
  64 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
  65 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  66 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  67 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  68 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
  69                                 | DDRCDR_PZ_LOZ \
  70                                 | DDRCDR_NZ_LOZ \
  71                                 | DDRCDR_ODT \
  72                                 | DDRCDR_Q_DRN)
  73                                 /* 0x7b880001 */
  74 /*
  75  * Manually set up DDR parameters
  76  * consist of one chip NT5TU64M16HG from NANYA
  77  */
  78
  79 #define CONFIG_SYS_DDR_SIZE             128 /* MB */
  80
  81 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
  82 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
  83                                 | CSCONFIG_ODT_RD_NEVER \
  84                                 | CSCONFIG_ODT_WR_ONLY_CURRENT \
  85                                 | CSCONFIG_BANK_BIT_3 \
  86                                 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
  87                                 /* 0x80010102 */
  88 #define CONFIG_SYS_DDR_TIMING_3 0
  89 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  90                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
  91                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
  92                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
  93                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  94                                 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  95                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  96                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  97                                 /* 0x00260802 */
  98 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
  99                                 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 100                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
 101                                 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
 102                                 | (9 << TIMING_CFG1_REFREC_SHIFT) \
 103                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
 104                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 105                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
 106                                 /* 0x26279222 */
 107 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
 108                                 | (4 << TIMING_CFG2_CPO_SHIFT) \
 109                                 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 110                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 111                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 112                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 113                                 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
 114                                 /* 0x021848c5 */
 115 #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
 116                                 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 117                                 /* 0x08240100 */
 118 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
 119                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 120                                 | SDRAM_CFG_DBW_16)
 121                                 /* 0x43100000 */
 122
 123 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000 /* 1 posted refresh */
 124 #define CONFIG_SYS_DDR_MODE             ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
 125                                 | (0x0242 << SDRAM_MODE_SD_SHIFT))
 126                                 /* ODT 150ohm CL=4, AL=0 on SDRAM */
 127 #define CONFIG_SYS_DDR_MODE2            0x00000000
 128
 129 /*
 130  * Memory test
 131  */
 132 #define CONFIG_SYS_MEMTEST_START        0x00001000 /* memtest region */
 133 #define CONFIG_SYS_MEMTEST_END          0x07f00000
 134
 135 /*
 136  * The reserved memory
 137  */
 138 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
 139
 140 #define CONFIG_SYS_MONITOR_LEN  (384 * 1024) /* Reserve 384 kB for Mon */
 141 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
 142
 143 /*
 144  * Initial RAM Base Address Setup
 145  */
 146 #define CONFIG_SYS_INIT_RAM_LOCK        1
 147 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 148 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 149 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 150         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 151
 152 /*
 153  * Local Bus Configuration & Clock Setup
 154  */
 155 #define CONFIG_SYS_LCRR_DBYP            LCRR_DBYP
 156 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
 157 #define CONFIG_SYS_LBC_LBCR             0x00040000
 158
 159 /*
 160  * FLASH on the Local Bus
 161  */
 162 #if 1
 163 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 164 #define CONFIG_FLASH_CFI_LEGACY
 165 #define CONFIG_SYS_FLASH_LEGACY_512Kx16
 166 #endif
 167
 168 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* FLASH base address */
 169 #define CONFIG_SYS_FLASH_SIZE           8 /* FLASH size is up to 8M */
 170
 171
 172 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 173 #define CONFIG_SYS_MAX_FLASH_SECT       135
 174
 175 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000 /* Flash Erase Timeout (ms) */
 176 #define CONFIG_SYS_FLASH_WRITE_TOUT     500 /* Flash Write Timeout (ms) */
 177
 178 /*
 179  * FPGA
 180  */
 181 #define CONFIG_SYS_FPGA0_BASE           0xE0600000
 182 #define CONFIG_SYS_FPGA0_SIZE           1 /* FPGA size is 1M */
 183
 184
 185 #define CONFIG_SYS_FPGA_BASE(k)         CONFIG_SYS_FPGA0_BASE
 186 #define CONFIG_SYS_FPGA_DONE(k)         0x0010
 187
 188 #define CONFIG_SYS_FPGA_COUNT           1
 189
 190 #define CONFIG_SYS_MCLINK_MAX           3
 191
 192 #define CONFIG_SYS_FPGA_PTR \
 193         { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
 194
 195 /*
 196  * Serial Port
 197  */
 198 #define CONFIG_SYS_NS16550_SERIAL
 199 #define CONFIG_SYS_NS16550_REG_SIZE     1
 200 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 201
 202 #define CONFIG_SYS_BAUDRATE_TABLE  \
 203         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 204
 205 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
 206 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
 207
 208 /* Pass open firmware flat tree */
 209
 210 /* I2C */
 211 #define CONFIG_SYS_I2C
 212 #define CONFIG_SYS_I2C_FSL
 213 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 214 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 215 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 216
 217 #define CONFIG_PCA953X                  /* NXP PCA9554 */
 218 #define CONFIG_PCA9698                  /* NXP PCA9698 */
 219
 220 #define CONFIG_SYS_I2C_IHS
 221 #define CONFIG_SYS_I2C_IHS_CH0
 222 #define CONFIG_SYS_I2C_IHS_SPEED_0              50000
 223 #define CONFIG_SYS_I2C_IHS_SLAVE_0              0x7F
 224 #define CONFIG_SYS_I2C_IHS_CH1
 225 #define CONFIG_SYS_I2C_IHS_SPEED_1              50000
 226 #define CONFIG_SYS_I2C_IHS_SLAVE_1              0x7F
 227 #define CONFIG_SYS_I2C_IHS_CH2
 228 #define CONFIG_SYS_I2C_IHS_SPEED_2              50000
 229 #define CONFIG_SYS_I2C_IHS_SLAVE_2              0x7F
 230 #define CONFIG_SYS_I2C_IHS_CH3
 231 #define CONFIG_SYS_I2C_IHS_SPEED_3              50000
 232 #define CONFIG_SYS_I2C_IHS_SLAVE_3              0x7F
 233
 234 #ifdef CONFIG_HRCON_DH
 235 #define CONFIG_SYS_I2C_IHS_DUAL
 236 #define CONFIG_SYS_I2C_IHS_CH0_1
 237 #define CONFIG_SYS_I2C_IHS_SPEED_0_1            50000
 238 #define CONFIG_SYS_I2C_IHS_SLAVE_0_1            0x7F
 239 #define CONFIG_SYS_I2C_IHS_CH1_1
 240 #define CONFIG_SYS_I2C_IHS_SPEED_1_1            50000
 241 #define CONFIG_SYS_I2C_IHS_SLAVE_1_1            0x7F
 242 #define CONFIG_SYS_I2C_IHS_CH2_1
 243 #define CONFIG_SYS_I2C_IHS_SPEED_2_1            50000
 244 #define CONFIG_SYS_I2C_IHS_SLAVE_2_1            0x7F
 245 #define CONFIG_SYS_I2C_IHS_CH3_1
 246 #define CONFIG_SYS_I2C_IHS_SPEED_3_1            50000
 247 #define CONFIG_SYS_I2C_IHS_SLAVE_3_1            0x7F
 248 #endif
 249
 250 /*
 251  * Software (bit-bang) I2C driver configuration
 252  */
 253 #define CONFIG_SYS_I2C_SOFT
 254 #define CONFIG_SYS_I2C_SOFT_SPEED               50000
 255 #define CONFIG_SYS_I2C_SOFT_SLAVE               0x7F
 256 #define I2C_SOFT_DECLARATIONS2
 257 #define CONFIG_SYS_I2C_SOFT_SPEED_2             50000
 258 #define CONFIG_SYS_I2C_SOFT_SLAVE_2             0x7F
 259 #define I2C_SOFT_DECLARATIONS3
 260 #define CONFIG_SYS_I2C_SOFT_SPEED_3             50000
 261 #define CONFIG_SYS_I2C_SOFT_SLAVE_3             0x7F
 262 #define I2C_SOFT_DECLARATIONS4
 263 #define CONFIG_SYS_I2C_SOFT_SPEED_4             50000
 264 #define CONFIG_SYS_I2C_SOFT_SLAVE_4             0x7F
 265 #define I2C_SOFT_DECLARATIONS5
 266 #define CONFIG_SYS_I2C_SOFT_SPEED_5             50000
 267 #define CONFIG_SYS_I2C_SOFT_SLAVE_5             0x7F
 268 #define I2C_SOFT_DECLARATIONS6
 269 #define CONFIG_SYS_I2C_SOFT_SPEED_6             50000
 270 #define CONFIG_SYS_I2C_SOFT_SLAVE_6             0x7F
 271 #define I2C_SOFT_DECLARATIONS7
 272 #define CONFIG_SYS_I2C_SOFT_SPEED_7             50000
 273 #define CONFIG_SYS_I2C_SOFT_SLAVE_7             0x7F
 274 #define I2C_SOFT_DECLARATIONS8
 275 #define CONFIG_SYS_I2C_SOFT_SPEED_8             50000
 276 #define CONFIG_SYS_I2C_SOFT_SLAVE_8             0x7F
 277
 278 #ifdef CONFIG_HRCON_DH
 279 #define I2C_SOFT_DECLARATIONS9
 280 #define CONFIG_SYS_I2C_SOFT_SPEED_9             50000
 281 #define CONFIG_SYS_I2C_SOFT_SLAVE_9             0x7F
 282 #define I2C_SOFT_DECLARATIONS10
 283 #define CONFIG_SYS_I2C_SOFT_SPEED_10            50000
 284 #define CONFIG_SYS_I2C_SOFT_SLAVE_10            0x7F
 285 #define I2C_SOFT_DECLARATIONS11
 286 #define CONFIG_SYS_I2C_SOFT_SPEED_11            50000
 287 #define CONFIG_SYS_I2C_SOFT_SLAVE_11            0x7F
 288 #define I2C_SOFT_DECLARATIONS12
 289 #define CONFIG_SYS_I2C_SOFT_SPEED_12            50000
 290 #define CONFIG_SYS_I2C_SOFT_SLAVE_12            0x7F
 291 #endif
 292
 293 #ifdef CONFIG_HRCON_DH
 294 #define CONFIG_SYS_ICS8N3QV01_I2C               {13, 14, 15, 16, 17, 18, 19, 20}
 295 #define CONFIG_SYS_DP501_I2C                    {1, 3, 5, 7, 2, 4, 6, 8}
 296 #define CONFIG_HRCON_FANS                       { {10, 0x4c}, {11, 0x4c}, \
 297                                                   {12, 0x4c} }
 298 #else
 299 #define CONFIG_SYS_ICS8N3QV01_I2C               {9, 10, 11, 12}
 300 #define CONFIG_SYS_DP501_I2C                    {1, 2, 3, 4}
 301 #define CONFIG_HRCON_FANS                       { {6, 0x4c}, {7, 0x4c}, \
 302                                                   {8, 0x4c} }
 303 #endif
 304
 305 #ifndef __ASSEMBLY__
 306 void fpga_gpio_set(unsigned int bus, int pin);
 307 void fpga_gpio_clear(unsigned int bus, int pin);
 308 int fpga_gpio_get(unsigned int bus, int pin);
 309 void fpga_control_set(unsigned int bus, int pin);
 310 void fpga_control_clear(unsigned int bus, int pin);
 311 #endif
 312
 313 #define I2C_SDA_GPIO    ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200)
 314 #define I2C_SCL_GPIO    ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100)
 315 #define I2C_FPGA_IDX    (I2C_ADAP_HWNR % 4)
 316
 317 #ifdef CONFIG_HRCON_DH
 318 #define I2C_ACTIVE \
 319         do { \
 320                 if (I2C_ADAP_HWNR > 7) \
 321                         fpga_control_set(I2C_FPGA_IDX, 0x0004); \
 322                 else \
 323                         fpga_control_clear(I2C_FPGA_IDX, 0x0004); \
 324         } while (0)
 325 #else
 326 #define I2C_ACTIVE      { }
 327 #endif
 328 #define I2C_TRISTATE    { }
 329 #define I2C_READ \
 330         (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
 331 #define I2C_SDA(bit) \
 332         do { \
 333                 if (bit) \
 334                         fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \
 335                 else \
 336                         fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \
 337         } while (0)
 338 #define I2C_SCL(bit) \
 339         do { \
 340                 if (bit) \
 341                         fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \
 342                 else \
 343                         fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \
 344         } while (0)
 345 #define I2C_DELAY       udelay(25)      /* 1/4 I2C clock duration */
 346
 347 /*
 348  * Software (bit-bang) MII driver configuration
 349  */
 350 #define CONFIG_BITBANGMII               /* bit-bang MII PHY management */
 351 #define CONFIG_BITBANGMII_MULTI
 352
 353 /*
 354  * OSD Setup
 355  */
 356 #define CONFIG_SYS_OSD_SCREENS          1
 357 #define CONFIG_SYS_DP501_DIFFERENTIAL
 358 #define CONFIG_SYS_DP501_VCAPCTRL0      0x01 /* DDR mode 0, DE for H/VSYNC */
 359
 360 #ifdef CONFIG_HRCON_DH
 361 #define CONFIG_SYS_OSD_DH
 362 #endif
 363
 364 /*
 365  * General PCI
 366  * Addresses are mapped 1-1.
 367  */
 368 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
 369 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA0000000
 370 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA0000000
 371 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
 372 #define CONFIG_SYS_PCIE1_CFG_BASE       0xB0000000
 373 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x01000000
 374 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 375 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB1000000
 376 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
 377
 378 /* enable PCIE clock */
 379 #define CONFIG_SYS_SCCR_PCIEXP1CM       1
 380
 381 #define CONFIG_PCI_INDIRECT_BRIDGE
 382 #define CONFIG_PCIE
 383
 384 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 385 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
 386
 387 /*
 388  * TSEC
 389  */
 390 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 391 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 392
 393 /*
 394  * TSEC ethernet configuration
 395  */
 396 #define CONFIG_TSEC1
 397 #define CONFIG_TSEC1_NAME       "eTSEC0"
 398 #define TSEC1_PHY_ADDR          1
 399 #define TSEC1_PHYIDX            0
 400 #define TSEC1_FLAGS             TSEC_GIGABIT
 401
 402 /* Options are: eTSEC[0-1] */
 403 #define CONFIG_ETHPRIME         "eTSEC0"
 404
 405 /*
 406  * Environment
 407  */
 408 #if 1
 409 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 410                                  CONFIG_SYS_MONITOR_LEN)
 411 #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K(one sector) for env */
 412 #define CONFIG_ENV_SIZE         0x2000
 413 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 414 #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
 415 #else
 416 #define CONFIG_ENV_SIZE         0x2000          /* 8KB */
 417 #endif
 418
 419 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 420 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 421
 422 /*
 423  * Command line configuration.
 424  */
 425
 426 /*
 427  * Miscellaneous configurable options
 428  */
 429 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
 430 #define CONFIG_SYS_HZ           1000    /* decrementer freq: 1ms ticks */
 431
 432 #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 433
 434 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 435
 436 /*
 437  * For booting Linux, the board info and command line data
 438  * have to be in the first 256 MB of memory, since this is
 439  * the maximum mapped by the Linux kernel during initialization.
 440  */
 441 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
 442
 443 /*
 444  * Environment Configuration
 445  */
 446
 447 #define CONFIG_ENV_OVERWRITE
 448
 449 #if defined(CONFIG_TSEC_ENET)
 450 #define CONFIG_HAS_ETH0
 451 #endif
 452
 453 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 454
 455
 456 #define CONFIG_HOSTNAME         "hrcon"
 457 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 458 #define CONFIG_BOOTFILE         "uImage"
 459
 460 #define CONFIG_PREBOOT          /* enable preboot variable */
 461
 462 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 463         "netdev=eth0\0"                                                 \
 464         "consoledev=ttyS1\0"                                            \
 465         "u-boot=u-boot.bin\0"                                           \
 466         "kernel_addr=1000000\0"                                 \
 467         "fdt_addr=C00000\0"                                             \
 468         "fdtfile=hrcon.dtb\0"                           \
 469         "load=tftp ${loadaddr} ${u-boot}\0"                             \
 470         "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)      \
 471                 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
 472                 " +${filesize};cp.b ${fileaddr} "                       \
 473                 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"   \
 474         "upd=run load update\0"                                         \
 475
 476 #define CONFIG_NFSBOOTCOMMAND                                           \
 477         "setenv bootargs root=/dev/nfs rw "                             \
 478         "nfsroot=$serverip:$rootpath "                                  \
 479         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 480         "console=$consoledev,$baudrate $othbootargs;"                   \
 481         "tftp ${kernel_addr} $bootfile;"                                \
 482         "tftp ${fdt_addr} $fdtfile;"                                    \
 483         "bootm ${kernel_addr} - ${fdt_addr}"
 484
 485 #define CONFIG_MMCBOOTCOMMAND                                           \
 486         "setenv bootargs root=/dev/mmcblk0p3 rw rootwait "              \
 487         "console=$consoledev,$baudrate $othbootargs;"                   \
 488         "ext2load mmc 0:2 ${kernel_addr} $bootfile;"                    \
 489         "ext2load mmc 0:2 ${fdt_addr} $fdtfile;"                        \
 490         "bootm ${kernel_addr} - ${fdt_addr}"
 491
 492 #define CONFIG_BOOTCOMMAND              CONFIG_MMCBOOTCOMMAND
 493
 494 #endif  /* __CONFIG_H */