include/configs/hrcon.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2014
   4  * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
   5  *
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 /*
  12  * High Level Configuration Options
  13  */
  14 #define CONFIG_E300             1 /* E300 family */
  15
  16 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC83xx_ESDHC_ADDR
  17
  18 /*
  19  * System IO Config
  20  */
  21 #define CONFIG_SYS_SICRH (\
  22         SICRH_ESDHC_A_SD |\
  23         SICRH_ESDHC_B_SD |\
  24         SICRH_ESDHC_C_SD |\
  25         SICRH_GPIO_A_GPIO |\
  26         SICRH_GPIO_B_GPIO |\
  27         SICRH_IEEE1588_A_GPIO |\
  28         SICRH_USB |\
  29         SICRH_GTM_GPIO |\
  30         SICRH_IEEE1588_B_GPIO |\
  31         SICRH_ETSEC2_GPIO |\
  32         SICRH_GPIOSEL_1 |\
  33         SICRH_TMROBI_V3P3 |\
  34         SICRH_TSOBI1_V2P5 |\
  35         SICRH_TSOBI2_V2P5)      /* 0x0037f103 */
  36 #define CONFIG_SYS_SICRL (\
  37         SICRL_SPI_PF0 |\
  38         SICRL_UART_PF0 |\
  39         SICRL_IRQ_PF0 |\
  40         SICRL_I2C2_PF0 |\
  41         SICRL_ETSEC1_GTX_CLK125)        /* 0x00000000 */
  42
  43 /*
  44  * SERDES
  45  */
  46 #define CONFIG_FSL_SERDES
  47 #define CONFIG_FSL_SERDES1      0xe3000
  48
  49 /*
  50  * Arbiter Setup
  51  */
  52 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
  53 #define CONFIG_SYS_ACR_RPTCNT   3 /* Arbiter repeat count is 4 */
  54 #define CONFIG_SYS_SPCR_TSECEP  3 /* eTSEC emergency priority is highest */
  55
  56 /*
  57  * DDR Setup
  58  */
  59 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
  60 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  61 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  62 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  63 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
  64                                 | DDRCDR_PZ_LOZ \
  65                                 | DDRCDR_NZ_LOZ \
  66                                 | DDRCDR_ODT \
  67                                 | DDRCDR_Q_DRN)
  68                                 /* 0x7b880001 */
  69 /*
  70  * Manually set up DDR parameters
  71  * consist of one chip NT5TU64M16HG from NANYA
  72  */
  73
  74 #define CONFIG_SYS_DDR_SIZE             128 /* MB */
  75
  76 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
  77 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
  78                                 | CSCONFIG_ODT_RD_NEVER \
  79                                 | CSCONFIG_ODT_WR_ONLY_CURRENT \
  80                                 | CSCONFIG_BANK_BIT_3 \
  81                                 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
  82                                 /* 0x80010102 */
  83 #define CONFIG_SYS_DDR_TIMING_3 0
  84 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  85                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
  86                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
  87                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
  88                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  89                                 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  90                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  91                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  92                                 /* 0x00260802 */
  93 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
  94                                 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  95                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
  96                                 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
  97                                 | (9 << TIMING_CFG1_REFREC_SHIFT) \
  98                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
  99                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 100                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
 101                                 /* 0x26279222 */
 102 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
 103                                 | (4 << TIMING_CFG2_CPO_SHIFT) \
 104                                 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 105                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 106                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 107                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 108                                 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
 109                                 /* 0x021848c5 */
 110 #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
 111                                 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 112                                 /* 0x08240100 */
 113 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
 114                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 115                                 | SDRAM_CFG_DBW_16)
 116                                 /* 0x43100000 */
 117
 118 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000 /* 1 posted refresh */
 119 #define CONFIG_SYS_DDR_MODE             ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
 120                                 | (0x0242 << SDRAM_MODE_SD_SHIFT))
 121                                 /* ODT 150ohm CL=4, AL=0 on SDRAM */
 122 #define CONFIG_SYS_DDR_MODE2            0x00000000
 123
 124 /*
 125  * Memory test
 126  */
 127 #define CONFIG_SYS_MEMTEST_START        0x00001000 /* memtest region */
 128 #define CONFIG_SYS_MEMTEST_END          0x07f00000
 129
 130 /*
 131  * The reserved memory
 132  */
 133 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
 134
 135 #define CONFIG_SYS_MONITOR_LEN  (384 * 1024) /* Reserve 384 kB for Mon */
 136 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
 137
 138 /*
 139  * Initial RAM Base Address Setup
 140  */
 141 #define CONFIG_SYS_INIT_RAM_LOCK        1
 142 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 143 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 144 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 145         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 146
 147 /*
 148  * Local Bus Configuration & Clock Setup
 149  */
 150 #define CONFIG_SYS_LCRR_DBYP            LCRR_DBYP
 151 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
 152 #define CONFIG_SYS_LBC_LBCR             0x00040000
 153
 154 /*
 155  * FLASH on the Local Bus
 156  */
 157 #if 1
 158 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 159 #define CONFIG_FLASH_CFI_LEGACY
 160 #define CONFIG_SYS_FLASH_LEGACY_512Kx16
 161 #endif
 162
 163 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* FLASH base address */
 164 #define CONFIG_SYS_FLASH_SIZE           8 /* FLASH size is up to 8M */
 165
 166
 167 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 168 #define CONFIG_SYS_MAX_FLASH_SECT       135
 169
 170 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000 /* Flash Erase Timeout (ms) */
 171 #define CONFIG_SYS_FLASH_WRITE_TOUT     500 /* Flash Write Timeout (ms) */
 172
 173 /*
 174  * FPGA
 175  */
 176 #define CONFIG_SYS_FPGA0_BASE           0xE0600000
 177 #define CONFIG_SYS_FPGA0_SIZE           1 /* FPGA size is 1M */
 178
 179
 180 #define CONFIG_SYS_FPGA_BASE(k)         CONFIG_SYS_FPGA0_BASE
 181 #define CONFIG_SYS_FPGA_DONE(k)         0x0010
 182
 183 #define CONFIG_SYS_FPGA_COUNT           1
 184
 185 #define CONFIG_SYS_MCLINK_MAX           3
 186
 187 #define CONFIG_SYS_FPGA_PTR \
 188         { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
 189
 190 /*
 191  * Serial Port
 192  */
 193 #define CONFIG_SYS_NS16550_SERIAL
 194 #define CONFIG_SYS_NS16550_REG_SIZE     1
 195 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 196
 197 #define CONFIG_SYS_BAUDRATE_TABLE  \
 198         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 199
 200 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
 201 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
 202
 203 /* Pass open firmware flat tree */
 204
 205 /* I2C */
 206 #define CONFIG_SYS_I2C
 207 #define CONFIG_SYS_I2C_FSL
 208 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 209 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 210 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 211
 212 #define CONFIG_PCA953X                  /* NXP PCA9554 */
 213 #define CONFIG_PCA9698                  /* NXP PCA9698 */
 214
 215 #define CONFIG_SYS_I2C_IHS
 216 #define CONFIG_SYS_I2C_IHS_CH0
 217 #define CONFIG_SYS_I2C_IHS_SPEED_0              50000
 218 #define CONFIG_SYS_I2C_IHS_SLAVE_0              0x7F
 219 #define CONFIG_SYS_I2C_IHS_CH1
 220 #define CONFIG_SYS_I2C_IHS_SPEED_1              50000
 221 #define CONFIG_SYS_I2C_IHS_SLAVE_1              0x7F
 222 #define CONFIG_SYS_I2C_IHS_CH2
 223 #define CONFIG_SYS_I2C_IHS_SPEED_2              50000
 224 #define CONFIG_SYS_I2C_IHS_SLAVE_2              0x7F
 225 #define CONFIG_SYS_I2C_IHS_CH3
 226 #define CONFIG_SYS_I2C_IHS_SPEED_3              50000
 227 #define CONFIG_SYS_I2C_IHS_SLAVE_3              0x7F
 228
 229 #ifdef CONFIG_HRCON_DH
 230 #define CONFIG_SYS_I2C_IHS_DUAL
 231 #define CONFIG_SYS_I2C_IHS_CH0_1
 232 #define CONFIG_SYS_I2C_IHS_SPEED_0_1            50000
 233 #define CONFIG_SYS_I2C_IHS_SLAVE_0_1            0x7F
 234 #define CONFIG_SYS_I2C_IHS_CH1_1
 235 #define CONFIG_SYS_I2C_IHS_SPEED_1_1            50000
 236 #define CONFIG_SYS_I2C_IHS_SLAVE_1_1            0x7F
 237 #define CONFIG_SYS_I2C_IHS_CH2_1
 238 #define CONFIG_SYS_I2C_IHS_SPEED_2_1            50000
 239 #define CONFIG_SYS_I2C_IHS_SLAVE_2_1            0x7F
 240 #define CONFIG_SYS_I2C_IHS_CH3_1
 241 #define CONFIG_SYS_I2C_IHS_SPEED_3_1            50000
 242 #define CONFIG_SYS_I2C_IHS_SLAVE_3_1            0x7F
 243 #endif
 244
 245 /*
 246  * Software (bit-bang) I2C driver configuration
 247  */
 248 #define CONFIG_SYS_I2C_SOFT
 249 #define CONFIG_SYS_I2C_SOFT_SPEED               50000
 250 #define CONFIG_SYS_I2C_SOFT_SLAVE               0x7F
 251 #define I2C_SOFT_DECLARATIONS2
 252 #define CONFIG_SYS_I2C_SOFT_SPEED_2             50000
 253 #define CONFIG_SYS_I2C_SOFT_SLAVE_2             0x7F
 254 #define I2C_SOFT_DECLARATIONS3
 255 #define CONFIG_SYS_I2C_SOFT_SPEED_3             50000
 256 #define CONFIG_SYS_I2C_SOFT_SLAVE_3             0x7F
 257 #define I2C_SOFT_DECLARATIONS4
 258 #define CONFIG_SYS_I2C_SOFT_SPEED_4             50000
 259 #define CONFIG_SYS_I2C_SOFT_SLAVE_4             0x7F
 260 #define I2C_SOFT_DECLARATIONS5
 261 #define CONFIG_SYS_I2C_SOFT_SPEED_5             50000
 262 #define CONFIG_SYS_I2C_SOFT_SLAVE_5             0x7F
 263 #define I2C_SOFT_DECLARATIONS6
 264 #define CONFIG_SYS_I2C_SOFT_SPEED_6             50000
 265 #define CONFIG_SYS_I2C_SOFT_SLAVE_6             0x7F
 266 #define I2C_SOFT_DECLARATIONS7
 267 #define CONFIG_SYS_I2C_SOFT_SPEED_7             50000
 268 #define CONFIG_SYS_I2C_SOFT_SLAVE_7             0x7F
 269 #define I2C_SOFT_DECLARATIONS8
 270 #define CONFIG_SYS_I2C_SOFT_SPEED_8             50000
 271 #define CONFIG_SYS_I2C_SOFT_SLAVE_8             0x7F
 272
 273 #ifdef CONFIG_HRCON_DH
 274 #define I2C_SOFT_DECLARATIONS9
 275 #define CONFIG_SYS_I2C_SOFT_SPEED_9             50000
 276 #define CONFIG_SYS_I2C_SOFT_SLAVE_9             0x7F
 277 #define I2C_SOFT_DECLARATIONS10
 278 #define CONFIG_SYS_I2C_SOFT_SPEED_10            50000
 279 #define CONFIG_SYS_I2C_SOFT_SLAVE_10            0x7F
 280 #define I2C_SOFT_DECLARATIONS11
 281 #define CONFIG_SYS_I2C_SOFT_SPEED_11            50000
 282 #define CONFIG_SYS_I2C_SOFT_SLAVE_11            0x7F
 283 #define I2C_SOFT_DECLARATIONS12
 284 #define CONFIG_SYS_I2C_SOFT_SPEED_12            50000
 285 #define CONFIG_SYS_I2C_SOFT_SLAVE_12            0x7F
 286 #endif
 287
 288 #ifdef CONFIG_HRCON_DH
 289 #define CONFIG_SYS_ICS8N3QV01_I2C               {13, 14, 15, 16, 17, 18, 19, 20}
 290 #define CONFIG_SYS_DP501_I2C                    {1, 3, 5, 7, 2, 4, 6, 8}
 291 #define CONFIG_HRCON_FANS                       { {10, 0x4c}, {11, 0x4c}, \
 292                                                   {12, 0x4c} }
 293 #else
 294 #define CONFIG_SYS_ICS8N3QV01_I2C               {9, 10, 11, 12}
 295 #define CONFIG_SYS_DP501_I2C                    {1, 2, 3, 4}
 296 #define CONFIG_HRCON_FANS                       { {6, 0x4c}, {7, 0x4c}, \
 297                                                   {8, 0x4c} }
 298 #endif
 299
 300 #ifndef __ASSEMBLY__
 301 void fpga_gpio_set(unsigned int bus, int pin);
 302 void fpga_gpio_clear(unsigned int bus, int pin);
 303 int fpga_gpio_get(unsigned int bus, int pin);
 304 void fpga_control_set(unsigned int bus, int pin);
 305 void fpga_control_clear(unsigned int bus, int pin);
 306 #endif
 307
 308 #define I2C_SDA_GPIO    ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200)
 309 #define I2C_SCL_GPIO    ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100)
 310 #define I2C_FPGA_IDX    (I2C_ADAP_HWNR % 4)
 311
 312 #ifdef CONFIG_HRCON_DH
 313 #define I2C_ACTIVE \
 314         do { \
 315                 if (I2C_ADAP_HWNR > 7) \
 316                         fpga_control_set(I2C_FPGA_IDX, 0x0004); \
 317                 else \
 318                         fpga_control_clear(I2C_FPGA_IDX, 0x0004); \
 319         } while (0)
 320 #else
 321 #define I2C_ACTIVE      { }
 322 #endif
 323 #define I2C_TRISTATE    { }
 324 #define I2C_READ \
 325         (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
 326 #define I2C_SDA(bit) \
 327         do { \
 328                 if (bit) \
 329                         fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \
 330                 else \
 331                         fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \
 332         } while (0)
 333 #define I2C_SCL(bit) \
 334         do { \
 335                 if (bit) \
 336                         fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \
 337                 else \
 338                         fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \
 339         } while (0)
 340 #define I2C_DELAY       udelay(25)      /* 1/4 I2C clock duration */
 341
 342 /*
 343  * Software (bit-bang) MII driver configuration
 344  */
 345 #define CONFIG_BITBANGMII               /* bit-bang MII PHY management */
 346 #define CONFIG_BITBANGMII_MULTI
 347
 348 /*
 349  * OSD Setup
 350  */
 351 #define CONFIG_SYS_OSD_SCREENS          1
 352 #define CONFIG_SYS_DP501_DIFFERENTIAL
 353 #define CONFIG_SYS_DP501_VCAPCTRL0      0x01 /* DDR mode 0, DE for H/VSYNC */
 354
 355 #ifdef CONFIG_HRCON_DH
 356 #define CONFIG_SYS_OSD_DH
 357 #endif
 358
 359 /*
 360  * General PCI
 361  * Addresses are mapped 1-1.
 362  */
 363 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
 364 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA0000000
 365 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA0000000
 366 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
 367 #define CONFIG_SYS_PCIE1_CFG_BASE       0xB0000000
 368 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x01000000
 369 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 370 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB1000000
 371 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
 372
 373 /* enable PCIE clock */
 374 #define CONFIG_SYS_SCCR_PCIEXP1CM       1
 375
 376 #define CONFIG_PCI_INDIRECT_BRIDGE
 377 #define CONFIG_PCIE
 378
 379 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 380 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
 381
 382 /*
 383  * TSEC
 384  */
 385 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 386 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 387
 388 /*
 389  * TSEC ethernet configuration
 390  */
 391 #define CONFIG_TSEC1
 392 #define CONFIG_TSEC1_NAME       "eTSEC0"
 393 #define TSEC1_PHY_ADDR          1
 394 #define TSEC1_PHYIDX            0
 395 #define TSEC1_FLAGS             TSEC_GIGABIT
 396
 397 /* Options are: eTSEC[0-1] */
 398 #define CONFIG_ETHPRIME         "eTSEC0"
 399
 400 /*
 401  * Environment
 402  */
 403 #if 1
 404 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 405                                  CONFIG_SYS_MONITOR_LEN)
 406 #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K(one sector) for env */
 407 #define CONFIG_ENV_SIZE         0x2000
 408 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 409 #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
 410 #else
 411 #define CONFIG_ENV_SIZE         0x2000          /* 8KB */
 412 #endif
 413
 414 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 415 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 416
 417 /*
 418  * Command line configuration.
 419  */
 420
 421 /*
 422  * Miscellaneous configurable options
 423  */
 424 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
 425 #define CONFIG_SYS_HZ           1000    /* decrementer freq: 1ms ticks */
 426
 427 #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 428
 429 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 430
 431 /*
 432  * For booting Linux, the board info and command line data
 433  * have to be in the first 256 MB of memory, since this is
 434  * the maximum mapped by the Linux kernel during initialization.
 435  */
 436 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
 437
 438 /*
 439  * Environment Configuration
 440  */
 441
 442 #define CONFIG_ENV_OVERWRITE
 443
 444 #if defined(CONFIG_TSEC_ENET)
 445 #define CONFIG_HAS_ETH0
 446 #endif
 447
 448 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 449
 450
 451 #define CONFIG_HOSTNAME         "hrcon"
 452 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 453 #define CONFIG_BOOTFILE         "uImage"
 454
 455 #define CONFIG_PREBOOT          /* enable preboot variable */
 456
 457 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 458         "netdev=eth0\0"                                                 \
 459         "consoledev=ttyS1\0"                                            \
 460         "u-boot=u-boot.bin\0"                                           \
 461         "kernel_addr=1000000\0"                                 \
 462         "fdt_addr=C00000\0"                                             \
 463         "fdtfile=hrcon.dtb\0"                           \
 464         "load=tftp ${loadaddr} ${u-boot}\0"                             \
 465         "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)      \
 466                 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
 467                 " +${filesize};cp.b ${fileaddr} "                       \
 468                 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"   \
 469         "upd=run load update\0"                                         \
 470
 471 #define CONFIG_NFSBOOTCOMMAND                                           \
 472         "setenv bootargs root=/dev/nfs rw "                             \
 473         "nfsroot=$serverip:$rootpath "                                  \
 474         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 475         "console=$consoledev,$baudrate $othbootargs;"                   \
 476         "tftp ${kernel_addr} $bootfile;"                                \
 477         "tftp ${fdt_addr} $fdtfile;"                                    \
 478         "bootm ${kernel_addr} - ${fdt_addr}"
 479
 480 #define CONFIG_MMCBOOTCOMMAND                                           \
 481         "setenv bootargs root=/dev/mmcblk0p3 rw rootwait "              \
 482         "console=$consoledev,$baudrate $othbootargs;"                   \
 483         "ext2load mmc 0:2 ${kernel_addr} $bootfile;"                    \
 484         "ext2load mmc 0:2 ${fdt_addr} $fdtfile;"                        \
 485         "bootm ${kernel_addr} - ${fdt_addr}"
 486
 487 #define CONFIG_BOOTCOMMAND              CONFIG_MMCBOOTCOMMAND
 488
 489 #endif  /* __CONFIG_H */