3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
6 * SPDX-License-Identifier: GPL-2.0+
13 * High Level Configuration Options
15 #define CONFIG_E300 1 /* E300 family */
16 #define CONFIG_MPC83xx 1 /* MPC83xx family */
17 #define CONFIG_MPC830x 1 /* MPC830x family */
18 #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */
19 #define CONFIG_HRCON 1 /* HRCON board specific */
21 #define CONFIG_SYS_TEXT_BASE 0xFE000000
23 #define CONFIG_IDENT_STRING " hrcon 0.01"
26 #define CONFIG_BOARD_EARLY_INIT_F
27 #define CONFIG_BOARD_EARLY_INIT_R
28 #define CONFIG_LAST_STAGE_INIT
30 /* new uImage format support */
32 #define CONFIG_FIT_VERBOSE 1
35 #define CONFIG_FSL_ESDHC
36 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
37 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
39 #define CONFIG_CMD_MMC
40 #define CONFIG_GENERIC_MMC
41 #define CONFIG_DOS_PARTITION
42 #define CONFIG_CMD_EXT2
44 #define CONFIG_CMD_FPGAD
45 #define CONFIG_CMD_IOLOOP
50 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */
51 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
54 * Hardware Reset Configuration Word
55 * if CLKIN is 66.66MHz, then
56 * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
57 * We choose the A type silicon as default, so the core is 400Mhz.
59 #define CONFIG_SYS_HRCW_LOW (\
60 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
61 HRCWL_DDR_TO_SCB_CLK_2X1 |\
63 HRCWL_CSB_TO_CLKIN_4X1 |\
64 HRCWL_CORE_TO_CSB_3X1)
66 * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
67 * in 8308's HRCWH according to the manual, but original Freescale's
68 * code has them and I've expirienced some problems using the board
69 * with BDI3000 attached when I've tried to set these bits to zero
70 * (UART doesn't work after the 'reset run' command).
72 #define CONFIG_SYS_HRCW_HIGH (\
74 HRCWH_PCI1_ARBITER_ENABLE |\
76 HRCWH_FROM_0XFFF00100 |\
77 HRCWH_BOOTSEQ_DISABLE |\
78 HRCWH_SW_WATCHDOG_DISABLE |\
79 HRCWH_ROM_LOC_LOCAL_16BIT |\
80 HRCWH_RL_EXT_LEGACY |\
81 HRCWH_TSEC1M_IN_RGMII |\
82 HRCWH_TSEC2M_IN_RGMII |\
88 #define CONFIG_SYS_SICRH (\
94 SICRH_IEEE1588_A_GPIO |\
97 SICRH_IEEE1588_B_GPIO |\
102 SICRH_TSOBI2_V2P5) /* 0x0037f103 */
103 #define CONFIG_SYS_SICRL (\
108 SICRL_ETSEC1_GTX_CLK125) /* 0x00000000 */
113 #define CONFIG_SYS_IMMR 0xE0000000
118 #define CONFIG_FSL_SERDES
119 #define CONFIG_FSL_SERDES1 0xe3000
124 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
125 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
126 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
131 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
132 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
133 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
134 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
135 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
142 * Manually set up DDR parameters
143 * consist of one chip NT5TU64M16HG from NANYA
146 #define CONFIG_SYS_DDR_SIZE 128 /* MB */
148 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
149 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
150 | CSCONFIG_ODT_RD_NEVER \
151 | CSCONFIG_ODT_WR_ONLY_CURRENT \
152 | CSCONFIG_BANK_BIT_3 \
153 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
155 #define CONFIG_SYS_DDR_TIMING_3 0
156 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
157 | (0 << TIMING_CFG0_WRT_SHIFT) \
158 | (0 << TIMING_CFG0_RRT_SHIFT) \
159 | (0 << TIMING_CFG0_WWT_SHIFT) \
160 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
161 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
162 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
163 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
165 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
166 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
167 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
168 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
169 | (9 << TIMING_CFG1_REFREC_SHIFT) \
170 | (2 << TIMING_CFG1_WRREC_SHIFT) \
171 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
172 | (2 << TIMING_CFG1_WRTORD_SHIFT))
174 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
175 | (4 << TIMING_CFG2_CPO_SHIFT) \
176 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
177 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
178 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
179 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
180 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
182 #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
183 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
185 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
186 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
190 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
191 #define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
192 | (0x0242 << SDRAM_MODE_SD_SHIFT))
193 /* ODT 150ohm CL=4, AL=0 on SDRAM */
194 #define CONFIG_SYS_DDR_MODE2 0x00000000
199 #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */
200 #define CONFIG_SYS_MEMTEST_END 0x07f00000
203 * The reserved memory
205 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
207 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
208 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
211 * Initial RAM Base Address Setup
213 #define CONFIG_SYS_INIT_RAM_LOCK 1
214 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
215 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
216 #define CONFIG_SYS_GBL_DATA_OFFSET \
217 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
220 * Local Bus Configuration & Clock Setup
222 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
223 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
224 #define CONFIG_SYS_LBC_LBCR 0x00040000
227 * FLASH on the Local Bus
230 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
231 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
232 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
233 #define CONFIG_FLASH_CFI_LEGACY
234 #define CONFIG_SYS_FLASH_LEGACY_512Kx16
236 #define CONFIG_SYS_NO_FLASH
239 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
240 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */
241 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
243 /* Window base at flash base */
244 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
245 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
247 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
248 | BR_PS_16 /* 16 bit port */ \
249 | BR_MS_GPCM /* MSEL = GPCM */ \
251 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
260 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
261 #define CONFIG_SYS_MAX_FLASH_SECT 135
263 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
264 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
269 #define CONFIG_SYS_FPGA0_BASE 0xE0600000
270 #define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */
272 /* Window base at FPGA base */
273 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA0_BASE
274 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_1MB)
276 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \
277 | BR_PS_16 /* 16 bit port */ \
278 | BR_MS_GPCM /* MSEL = GPCM */ \
280 #define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \
289 #define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
290 #define CONFIG_SYS_FPGA_DONE(k) 0x0010
292 #define CONFIG_SYS_FPGA_COUNT 1
294 #define CONFIG_SYS_MCLINK_MAX 3
296 #define CONFIG_SYS_FPGA_PTR \
297 { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
302 #define CONFIG_CONS_INDEX 2
303 #define CONFIG_SYS_NS16550
304 #define CONFIG_SYS_NS16550_SERIAL
305 #define CONFIG_SYS_NS16550_REG_SIZE 1
306 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
308 #define CONFIG_SYS_BAUDRATE_TABLE \
309 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
311 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
312 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
314 /* Use the HUSH parser */
315 #define CONFIG_SYS_HUSH_PARSER
317 /* Pass open firmware flat tree */
318 #define CONFIG_OF_LIBFDT 1
319 #define CONFIG_OF_BOARD_SETUP 1
320 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
323 #define CONFIG_SYS_I2C
324 #define CONFIG_SYS_I2C_FSL
325 #define CONFIG_SYS_FSL_I2C_SPEED 400000
326 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
327 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
329 #define CONFIG_PCA953X /* NXP PCA9554 */
330 #define CONFIG_PCA9698 /* NXP PCA9698 */
332 #define CONFIG_SYS_I2C_IHS
333 #define CONFIG_SYS_I2C_IHS_CH0
334 #define CONFIG_SYS_I2C_IHS_SPEED_0 50000
335 #define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F
336 #define CONFIG_SYS_I2C_IHS_CH1
337 #define CONFIG_SYS_I2C_IHS_SPEED_1 50000
338 #define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F
339 #define CONFIG_SYS_I2C_IHS_CH2
340 #define CONFIG_SYS_I2C_IHS_SPEED_2 50000
341 #define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F
342 #define CONFIG_SYS_I2C_IHS_CH3
343 #define CONFIG_SYS_I2C_IHS_SPEED_3 50000
344 #define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F
347 * Software (bit-bang) I2C driver configuration
349 #define CONFIG_SYS_I2C_SOFT
350 #define CONFIG_SYS_I2C_SOFT_SPEED 50000
351 #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
352 #define I2C_SOFT_DECLARATIONS2
353 #define CONFIG_SYS_I2C_SOFT_SPEED_2 50000
354 #define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F
355 #define I2C_SOFT_DECLARATIONS3
356 #define CONFIG_SYS_I2C_SOFT_SPEED_3 50000
357 #define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F
358 #define I2C_SOFT_DECLARATIONS4
359 #define CONFIG_SYS_I2C_SOFT_SPEED_4 50000
360 #define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F
362 #define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8}
363 #define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8}
364 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
367 void fpga_gpio_set(unsigned int bus, int pin);
368 void fpga_gpio_clear(unsigned int bus, int pin);
369 int fpga_gpio_get(unsigned int bus, int pin);
372 #define I2C_ACTIVE { }
373 #define I2C_TRISTATE { }
375 (fpga_gpio_get(I2C_ADAP_HWNR, 0x0040) ? 1 : 0)
376 #define I2C_SDA(bit) \
379 fpga_gpio_set(I2C_ADAP_HWNR, 0x0040); \
381 fpga_gpio_clear(I2C_ADAP_HWNR, 0x0040); \
383 #define I2C_SCL(bit) \
386 fpga_gpio_set(I2C_ADAP_HWNR, 0x0020); \
388 fpga_gpio_clear(I2C_ADAP_HWNR, 0x0020); \
390 #define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */
393 * Software (bit-bang) MII driver configuration
395 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
396 #define CONFIG_BITBANGMII_MULTI
401 #define CONFIG_SYS_OSD_SCREENS 1
402 #define CONFIG_SYS_DP501_DIFFERENTIAL
403 #define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */
407 * Addresses are mapped 1-1.
409 #define CONFIG_SYS_PCIE1_BASE 0xA0000000
410 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
411 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
412 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
413 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
414 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
415 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
416 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
417 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
419 /* enable PCIE clock */
420 #define CONFIG_SYS_SCCR_PCIEXP1CM 1
423 #define CONFIG_PCI_INDIRECT_BRIDGE
426 #define CONFIG_PCI_PNP /* do pci plug-and-play */
428 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
429 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
434 #define CONFIG_TSEC_ENET /* TSEC ethernet support */
435 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
436 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
439 * TSEC ethernet configuration
441 #define CONFIG_MII 1 /* MII PHY management */
443 #define CONFIG_TSEC1_NAME "eTSEC0"
444 #define TSEC1_PHY_ADDR 1
445 #define TSEC1_PHYIDX 0
446 #define TSEC1_FLAGS TSEC_GIGABIT
448 /* Options are: eTSEC[0-1] */
449 #define CONFIG_ETHPRIME "eTSEC0"
455 #define CONFIG_ENV_IS_IN_FLASH 1
456 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
457 CONFIG_SYS_MONITOR_LEN)
458 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
459 #define CONFIG_ENV_SIZE 0x2000
460 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
461 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
463 #define CONFIG_ENV_IS_NOWHERE
464 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
467 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
468 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
471 * Command line configuration.
473 #define CONFIG_CMD_I2C
474 #define CONFIG_CMD_MII
475 #define CONFIG_CMD_PCI
476 #define CONFIG_CMD_PING
478 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
479 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
482 * Miscellaneous configurable options
484 #define CONFIG_SYS_LONGHELP /* undef to save memory */
485 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
486 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
488 #undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */
490 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
492 #define CONFIG_SYS_CONSOLE_INFO_QUIET
494 /* Print Buffer Size */
495 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
496 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
497 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
500 * For booting Linux, the board info and command line data
501 * have to be in the first 256 MB of memory, since this is
502 * the maximum mapped by the Linux kernel during initialization.
504 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
509 #define CONFIG_SYS_HID0_INIT 0x000000000
510 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
511 HID0_ENABLE_INSTRUCTION_CACHE | \
512 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
513 #define CONFIG_SYS_HID2 HID2_HBE
519 /* DDR: cache cacheable */
520 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
522 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
524 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
525 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
527 /* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */
528 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
529 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
530 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
532 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
533 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
535 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
536 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
538 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
540 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
541 BATL_CACHEINHIBIT | \
543 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
545 /* Stack in dcache: cacheable, no memory coherence */
546 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
547 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
549 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
550 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
553 * Environment Configuration
556 #define CONFIG_ENV_OVERWRITE
558 #if defined(CONFIG_TSEC_ENET)
559 #define CONFIG_HAS_ETH0
562 #define CONFIG_BAUDRATE 115200
564 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
566 #define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
568 #define CONFIG_HOSTNAME hrcon
569 #define CONFIG_ROOTPATH "/opt/nfsroot"
570 #define CONFIG_BOOTFILE "uImage"
572 #define CONFIG_PREBOOT /* enable preboot variable */
574 #define CONFIG_EXTRA_ENV_SETTINGS \
576 "consoledev=ttyS1\0" \
577 "u-boot=u-boot.bin\0" \
578 "kernel_addr=1000000\0" \
579 "fdt_addr=C00000\0" \
580 "fdtfile=hrcon.dtb\0" \
581 "load=tftp ${loadaddr} ${u-boot}\0" \
582 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
583 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
584 " +${filesize};cp.b ${fileaddr} " \
585 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
586 "upd=run load update\0" \
588 #define CONFIG_NFSBOOTCOMMAND \
589 "setenv bootargs root=/dev/nfs rw " \
590 "nfsroot=$serverip:$rootpath " \
591 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
592 "console=$consoledev,$baudrate $othbootargs;" \
593 "tftp ${kernel_addr} $bootfile;" \
594 "tftp ${fdt_addr} $fdtfile;" \
595 "bootm ${kernel_addr} - ${fdt_addr}"
597 #define CONFIG_MMCBOOTCOMMAND \
598 "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \
599 "console=$consoledev,$baudrate $othbootargs;" \
600 "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \
601 "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \
602 "bootm ${kernel_addr} - ${fdt_addr}"
604 #define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
607 #endif /* __CONFIG_H */