2 * (C) Copyright 2003-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * High Level Configuration Options
32 #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
33 #define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
34 #define CONFIG_HMI1001 1 /* HMI1001 board */
36 #define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
38 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
39 #define BOOTFLAG_WARM 0x02 /* Software reboot */
41 #define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
42 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
43 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
46 #define CONFIG_BOARD_EARLY_INIT_R
49 * Serial console configuration
51 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
52 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
53 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
58 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
66 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
67 #include <cmd_confdefs.h>
69 #define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
71 #if (TEXT_BASE == 0xFFF00000) /* Boot low */
72 # define CFG_LOWBOOT 1
78 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
80 #define CONFIG_PREBOOT "echo;" \
81 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
84 #undef CONFIG_BOOTARGS
86 #define CONFIG_EXTRA_ENV_SETTINGS \
88 "nfsargs=setenv bootargs root=/dev/nfs rw " \
89 "nfsroot=$(serverip):$(rootpath)\0" \
90 "ramargs=setenv bootargs root=/dev/ram rw\0" \
91 "addip=setenv bootargs $(bootargs) " \
92 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
93 ":$(hostname):$(netdev):off panic=1\0" \
94 "flash_nfs=run nfsargs addip;" \
95 "bootm $(kernel_addr)\0" \
96 "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
97 "rootpath=/opt/eldk/ppc_82xx\0" \
100 #define CONFIG_BOOTCOMMAND "run net_nfs"
103 * IPB Bus clocking configuration.
105 #undef CFG_IPBSPEED_133 /* define for 133MHz speed */
110 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
111 #define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
113 #define CFG_I2C_SPEED 100000 /* 100 kHz */
114 #define CFG_I2C_SLAVE 0x7F
117 * EEPROM configuration
119 #define CFG_I2C_EEPROM_ADDR 0x58
120 #define CFG_I2C_EEPROM_ADDR_LEN 1
121 #define CFG_EEPROM_PAGE_WRITE_BITS 4
122 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
127 #define CONFIG_RTC_PCF8563
128 #define CFG_I2C_RTC_ADDR 0x51
131 * Flash configuration
133 #define CFG_FLASH_BASE 0xFF800000
135 #define CFG_FLASH_SIZE 0x00800000 /* 8 MByte */
136 #define CFG_MAX_FLASH_SECT 67 /* max num of sects on one chip */
138 #define CFG_ENV_ADDR (TEXT_BASE+0x40000) /* second sector */
139 #define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks
141 #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
142 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
144 #define CFG_FLASH_CFI_DRIVER
145 #define CFG_FLASH_CFI
146 #define CFG_FLASH_EMPTY_INFO
147 #define CFG_FLASH_CFI_AMD_RESET
150 * Environment settings
152 #define CFG_ENV_IS_IN_FLASH 1
153 #define CFG_ENV_SIZE 0x4000
154 #define CFG_ENV_SECT_SIZE 0x20000
155 #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
156 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
161 #define CFG_MBAR 0xF0000000
162 #define CFG_SDRAM_BASE 0x00000000
163 #define CFG_DEFAULT_MBAR 0x80000000
165 /* Settings for XLB = 132 MHz */
167 #define SDRAM_MODE 0x018D0000
168 #define SDRAM_EMODE 0x40090000
169 #define SDRAM_CONTROL 0x714f0f00
170 #define SDRAM_CONFIG1 0x73722930
171 #define SDRAM_CONFIG2 0x47770000
172 #define SDRAM_TAPDELAY 0x10000000
174 /* Use ON-Chip SRAM until RAM will be available */
175 #define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
177 /* preserve space for the post_word at end of on-chip SRAM */
178 #define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
180 #define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE
184 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
185 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
186 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
188 #define CFG_MONITOR_BASE TEXT_BASE
189 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
190 # define CFG_RAMBOOT 1
193 #define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
194 #define CFG_MALLOC_LEN (512 << 10) /* Reserve 128 kB for malloc() */
195 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
198 * Ethernet configuration
200 #define CONFIG_MPC5xxx_FEC 1
201 #define CONFIG_PHY_ADDR 0x00
206 #define CFG_GPS_PORT_CONFIG 0x01051004
209 * Miscellaneous configurable options
211 #define CFG_LONGHELP /* undef to save memory */
212 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
213 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
214 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
216 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
218 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
219 #define CFG_MAXARGS 16 /* max number of command args */
220 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
222 /* Enable an alternate, more extensive memory test */
223 #define CFG_ALT_MEMTEST
225 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
226 #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
228 #define CFG_LOAD_ADDR 0x100000 /* default load address */
230 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
233 * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
234 * which is normally part of the default commands (CFV_CMD_DFL)
239 * Various low-level settings
241 #if defined(CONFIG_MPC5200)
242 #define CFG_HID0_INIT HID0_ICE | HID0_ICFI
243 #define CFG_HID0_FINAL HID0_ICE
245 #define CFG_HID0_INIT 0
246 #define CFG_HID0_FINAL 0
249 #define CFG_BOOTCS_START CFG_FLASH_BASE
250 #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
251 #define CFG_BOOTCS_CFG 0x0004FB00
252 #define CFG_CS0_START CFG_FLASH_BASE
253 #define CFG_CS0_SIZE CFG_FLASH_SIZE
255 /* 8Mbit SRAM @0x80100000 */
256 #define CFG_CS1_START 0x80100000
257 #define CFG_CS1_SIZE 0x00100000
258 #define CFG_CS1_CFG 0x19B00
260 /* FRAM 32Kbyte @0x80700000 */
261 #define CFG_CS2_START 0x80700000
262 #define CFG_CS2_SIZE 0x00008000
263 #define CFG_CS2_CFG 0x19800
265 /* Display H1, Status Inputs, EPLD @0x80600000 */
266 #define CFG_CS3_START 0x80600000
267 #define CFG_CS3_SIZE 0x00000210
268 #define CFG_CS3_CFG 0x9800
270 #define CFG_CS_BURST 0x00000000
271 #define CFG_CS_DEADCYCLE 0x33333333
273 #endif /* __CONFIG_H */