3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
9 * board/config.h - configuration options, board specific
16 * High Level Configuration Options
20 #define CONFIG_MPC860 1 /* This is a MPC860T CPU */
21 #define CONFIG_HERMES 1 /* ...on a HERMES-PRO board */
23 #define CONFIG_SYS_TEXT_BASE 0xFE000000
25 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
26 #undef CONFIG_8xx_CONS_SMC2
27 #undef CONFIG_8xx_CONS_NONE
28 #define CONFIG_BAUDRATE 9600
30 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
32 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
35 #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
37 #define CONFIG_BOARD_TYPES 1 /* support board types */
39 #define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */
41 #undef CONFIG_BOOTARGS
42 #define CONFIG_BOOTCOMMAND \
44 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
45 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
48 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
49 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
51 #undef CONFIG_WATCHDOG /* watchdog disabled */
55 * Command line configuration.
57 #include <config_cmd_default.h>
63 #define CONFIG_BOOTP_SUBNETMASK
64 #define CONFIG_BOOTP_GATEWAY
65 #define CONFIG_BOOTP_HOSTNAME
66 #define CONFIG_BOOTP_BOOTPATH
70 * Miscellaneous configurable options
72 #define CONFIG_SYS_LONGHELP /* undef to save memory */
73 #if defined(CONFIG_CMD_KGDB)
74 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
76 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
78 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
79 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
80 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
82 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
83 #define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
85 #define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
87 #define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
89 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
91 #define CONFIG_SYS_ALLOC_DPRAM 1 /* use allocation routines */
93 * Low Level Configuration Settings
94 * (address mappings, register initial values, etc.)
95 * You should know what you are doing if you make changes here.
97 /*-----------------------------------------------------------------------
98 * Internal Memory Mapped Register
100 #define CONFIG_SYS_IMMR 0xFF000000 /* Non-Standard value! */
102 /*-----------------------------------------------------------------------
103 * Definitions for initial stack pointer and data area (in DPRAM)
105 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
106 #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
107 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
108 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
110 /*-----------------------------------------------------------------------
111 * Start addresses for the final memory configuration
112 * (Set up by the startup code)
113 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
115 #define CONFIG_SYS_SDRAM_BASE 0x00000000
116 #define CONFIG_SYS_FLASH_BASE 0xFE000000
118 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
120 #define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
122 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
123 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
126 * For booting Linux, the board info and command line data
127 * have to be in the first 8 MB of memory, since this is
128 * the maximum mapped by the Linux kernel during initialization.
130 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
131 /*-----------------------------------------------------------------------
134 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
135 #define CONFIG_SYS_MAX_FLASH_SECT 124 /* max number of sectors on one chip */
137 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
138 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
140 #define CONFIG_ENV_IS_IN_FLASH 1
141 #define CONFIG_ENV_OFFSET 0x4000 /* Offset of Environment Sector */
142 #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
143 /*-----------------------------------------------------------------------
144 * Cache Configuration
146 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
147 #if defined(CONFIG_CMD_KGDB)
148 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
151 /*-----------------------------------------------------------------------
152 * SYPCR - System Protection Control 11-9
153 * SYPCR can only be written once after reset!
154 *-----------------------------------------------------------------------
155 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
158 #if defined(CONFIG_WATCHDOG)
159 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
160 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
162 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
165 /*-----------------------------------------------------------------------
166 * SIUMCR - SIU Module Configuration 11-6
167 *-----------------------------------------------------------------------
168 * +0x0000 => 0x000000C0
170 #define CONFIG_SYS_SIUMCR 0
172 /*-----------------------------------------------------------------------
173 * TBSCR - Time Base Status and Control 11-26
174 *-----------------------------------------------------------------------
175 * Clear Reference Interrupt Status, Timebase freezing enabled
178 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
180 /*-----------------------------------------------------------------------
181 * PISCR - Periodic Interrupt Status and Control 11-31
182 *-----------------------------------------------------------------------
183 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
186 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
188 /*-----------------------------------------------------------------------
189 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
190 *-----------------------------------------------------------------------
191 * Reset PLL lock status sticky bit, timer expired status bit and timer
192 * interrupt status bit, set PLL multiplication factor !
194 /* +0x0286 => 0x00B0D0C0 */
195 #define CONFIG_SYS_PLPRCR \
196 ( (11 << PLPRCR_MF_SHIFT) | \
197 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \
198 /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \
199 PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \
202 /*-----------------------------------------------------------------------
203 * SCCR - System Clock and reset Control Register 15-27
204 *-----------------------------------------------------------------------
205 * Set clock output, timebase and RTC source and divider,
206 * power management and some other internal clocks
208 #define SCCR_MASK SCCR_EBDF11
209 /* +0x0282 => 0x03800000 */
210 #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_TBS | \
211 SCCR_RTDIV | SCCR_RTSEL | \
212 /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
213 SCCR_EBDF00 | SCCR_DFSYNC00 | \
214 SCCR_DFBRG00 | SCCR_DFNL000 | \
217 /*-----------------------------------------------------------------------
218 * RTCSC - Real-Time Clock Status and Control Register 11-27
219 *-----------------------------------------------------------------------
221 /* +0x0220 => 0x00C3 */
222 #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
225 /*-----------------------------------------------------------------------
226 * RCCR - RISC Controller Configuration Register 19-4
227 *-----------------------------------------------------------------------
229 /* +0x09C4 => TIMEP=1 */
230 #define CONFIG_SYS_RCCR 0x0100
232 /*-----------------------------------------------------------------------
233 * RMDS - RISC Microcode Development Support Control Register
234 *-----------------------------------------------------------------------
236 #define CONFIG_SYS_RMDS 0
238 /*-----------------------------------------------------------------------
240 *-----------------------------------------------------------------------
243 #define CONFIG_SYS_DER 0
246 * Init Memory Controller:
248 * BR0 and OR0 (FLASH)
251 #define FLASH_BASE0_PRELIM 0xFE000000 /* FLASH bank #0 */
253 /* used to re-map FLASH
254 * restrict access enough to keep SRAM working (if any)
255 * but not too much to meddle with FLASH accesses
257 /* allow for max 4 MB of Flash */
258 #define CONFIG_SYS_REMAP_OR_AM 0xFFC00000 /* OR addr mask */
259 #define CONFIG_SYS_PRELIM_OR_AM 0xFFC00000 /* OR addr mask */
261 /* FLASH timing: ACS = 11, TRLX = 1, CSNT = 1, SCY = 5, EHTR = 0 */
262 #define CONFIG_SYS_OR_TIMING_FLASH ( OR_CSNT_SAM | /*OR_ACS_DIV4 |*/ OR_BI | \
263 OR_SCY_5_CLK | OR_TRLX)
265 #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
266 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
267 /* 8 bit, bank valid */
268 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
273 * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
275 #define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM bank */
276 #define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */
277 #define SDRAM_TIMING 0x00000A00 /* SDRAM-Timing */
279 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */
281 #define CONFIG_SYS_OR1_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
282 #define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
285 * BR2/OR2 - HPRO2: PEB2256 @ 0xE0000000, 8 Bit wide
287 #define HPRO2_BASE 0xE0000000
288 #define HPRO2_OR_AM 0xFFFF8000
289 #define HPRO2_TIMING 0x00000934
291 #define CONFIG_SYS_OR2 (HPRO2_OR_AM | HPRO2_TIMING)
292 #define CONFIG_SYS_BR2 ((HPRO2_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
303 * MAMR settings for SDRAM
306 /* periodic timer for refresh */
307 #define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */
310 #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
311 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
312 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
314 #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
315 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
316 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
317 #endif /* __CONFIG_H */