2 * (C) Copyright 2007 Netstal Maschinen AG
3 * Niklaus Giger (Niklaus.Giger@netstal.com)
5 * (C) Copyright 2006-2007
6 * Stefan Roese, DENX Software Engineering, sr@denx.de.
9 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
10 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 /************************************************************************
29 * hcu5.h - configuration for HCU5 board (derived from sequoia.h)
30 ***********************************************************************/
35 /*-----------------------------------------------------------------------
36 * High Level Configuration Options
37 *----------------------------------------------------------------------*/
38 #define CONFIG_HCU5 1 /* Board is HCU5 */
39 #define CONFIG_440EPX 1 /* Specific PPC440EPx */
40 #define CONFIG_440 1 /* ... PPC440 family */
41 #define CONFIG_4xx 1 /* ... PPC4xx family */
42 #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
44 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
45 #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
46 #define CONFIG_ADD_RAM_INFO 1 /* Print additional info */
48 /*-----------------------------------------------------------------------
49 * Base addresses -- Note these are effective addresses where the
50 * actual resources get mapped (not physical addresses)
51 *----------------------------------------------------------------------*/
52 #define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
53 #define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
55 #define CFG_BOOT_BASE_ADDR 0xfff00000
56 #define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
57 #define CFG_FLASH_BASE 0xfff80000 /* start of FLASH */
58 #define CFG_MONITOR_BASE TEXT_BASE
59 #define CFG_OCM_BASE 0xe0010000 /* ocm */
60 #define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */
61 #define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
62 #define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
63 #define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
64 #define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
66 /* Don't change either of these */
67 #define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
69 #define CFG_USB2D0_BASE 0xe0000100
70 #define CFG_USB_DEVICE 0xe0000000
71 #define CFG_USB_HOST 0xe0000400
73 /*-----------------------------------------------------------------------
74 * Initial RAM & stack pointer
75 *----------------------------------------------------------------------*/
76 /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
77 #define CFG_INIT_RAM_OCM 1 /* OCM as init ram */
78 #define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
80 #define CFG_INIT_RAM_END (4 << 10)
81 #define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
82 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
83 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
85 /*-----------------------------------------------------------------------
87 *----------------------------------------------------------------------*/
88 #undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
89 #define CONFIG_BAUDRATE 9600
90 #undef CONFIG_SERIAL_MULTI /* needed to be able to define
91 CONFIG_SERIAL_SOFTWARE_FIFO, but
92 CONFIG_SERIAL_SOFTWARE_FIFO (16) does not work */
93 /* Size (bytes) of interrupt driven serial port buffer.
94 * Set to 0 to use polling instead of interrupts.
95 * Setting to 0 will also disable RTS/CTS handshaking.
97 #undef CONFIG_SERIAL_SOFTWARE_FIFO
98 #undef CONFIG_UART1_CONSOLE
100 #define CFG_BAUDRATE_TABLE \
101 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
103 /*-----------------------------------------------------------------------
105 *----------------------------------------------------------------------*/
107 #undef CFG_ENV_IS_IN_NVRAM
108 #undef CFG_ENV_IS_IN_FLASH
109 #define CFG_ENV_IS_IN_EEPROM
110 #undef CFG_ENV_IS_NOWHERE
112 #ifdef CFG_ENV_IS_IN_EEPROM
113 /* Put the environment after the SDRAM and bootstrap configuration */
114 #define PROM_SIZE 2048
115 #define CFG_BOOSTRAP_OPTION_OFFSET 512
116 #define CFG_ENV_OFFSET (CFG_BOOSTRAP_OPTION_OFFSET + 0x10)
117 #define CFG_ENV_SIZE (PROM_SIZE-CFG_ENV_OFFSET)
120 #ifdef CFG_ENV_IS_IN_FLASH
121 /* Put the environment in Flash */
122 #define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
123 #define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
124 #define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
126 /* Address and size of Redundant Environment Sector */
127 #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
128 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
131 /*-----------------------------------------------------------------------
133 *----------------------------------------------------------------------*/
134 #define CFG_MBYTES_SDRAM (128) /* 128 MB or 256 MB */
135 #define CFG_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */
136 #undef CONFIG_DDR_DATA_EYE /* Do not use DDR2 optimization */
137 #define CONFIG_DDR_ECC 1 /* enable ECC */
139 /*-----------------------------------------------------------------------
140 * I2C stuff for a ATMEL AT24C16 (2kB holding ENV, we are using the
141 * the second internal I2C controller of the PPC440EPx
142 *----------------------------------------------------------------------*/
143 #define CFG_SPD_BUS_NUM 1
145 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
146 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
147 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
148 #define CFG_I2C_SLAVE 0x7F
150 /* This is the 7bit address of the device, not including P. */
151 #define CFG_I2C_EEPROM_ADDR 0x50
152 #define CFG_I2C_EEPROM_ADDR_LEN 1
154 /* The EEPROM can do 16byte ( 1 << 4 ) page writes. */
155 #define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
156 #define CFG_EEPROM_PAGE_WRITE_BITS 4
157 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
158 #define CFG_EEPROM_PAGE_WRITE_ENABLE
159 #undef CFG_I2C_MULTI_EEPROMS
162 #define CONFIG_PREBOOT "echo;" \
163 "echo Type \"run nfs\" to mount Linux root filesystem over NFS;"\
166 #undef CONFIG_BOOTARGS
168 /* Setup some board specific values for the default environment variables */
169 #define CONFIG_HOSTNAME hcu5
170 #define CONFIG_IPADDR 172.25.1.42
171 #define CONFIG_ETHADDR 00:60:13:00:00:00 /* Netstal Machines AG MAC */
172 #define CONFIG_OVERWRITE_ETHADDR_ONCE
173 #define CONFIG_SERVERIP 172.25.1.3
175 #define CFG_TFTP_LOADADDR 0x01000000 /* @16 MB */
177 #define CONFIG_EXTRA_ENV_SETTINGS \
179 "loadaddr=0x01000000\0" \
180 "nfsargs=setenv bootargs root=/dev/nfs rw " \
181 "nfsroot=${serverip}:${rootpath}\0" \
182 "ramargs=setenv bootargs root=/dev/ram rw\0" \
183 "addip=setenv bootargs ${bootargs} " \
184 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
185 ":${hostname}:${netdev}:off panic=1\0" \
186 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
187 "nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
189 "bootfile=hcu5/uImage\0" \
190 "rootpath=/home/hcu/eldk/ppc_4xxFP\0" \
191 "load=tftp 100000 hcu5/u-boot.bin\0" \
192 "update=protect off FFFa0000 FFFFFFFF;era FFFa0000 FFFFFFFF;" \
193 "cp.b 100000 FFFa0000 60000\0" \
194 "upd=run load;run update\0" \
195 "vx=tftp ${loadaddr} hcu5/hcu5_vx_rom;" \
196 "setenv bootargs emac(0,0)hcu5_vx_rom e=${ipaddr} " \
197 " h=${serverip} u=dpu pw=netstal8752 tn=hcu5 f=0x3008;" \
198 "bootvx ${loadaddr}\0" \
200 #define CONFIG_BOOTCOMMAND "run vx"
203 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
205 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
208 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
209 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
211 #define CONFIG_M88E1111_PHY 1
212 #define CONFIG_IBM_EMAC4_V4 1
213 #define CONFIG_MII 1 /* MII PHY management */
214 #define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
216 #define CONFIG_PHY_RESET 1 /* reset phy upon startup */
218 #define CONFIG_HAS_ETH0
219 #define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
221 #define CONFIG_NET_MULTI 1
222 #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
223 #define CONFIG_PHY1_ADDR 1
226 #define CONFIG_USB_OHCI
227 #define CONFIG_USB_STORAGE
229 /* Comment this out to enable USB 1.1 device */
230 #define USB_2_0_DEVICE
233 #define CONFIG_MAC_PARTITION
234 #define CONFIG_DOS_PARTITION
235 #define CONFIG_ISO_PARTITION
240 #define CONFIG_BOOTP_BOOTFILESIZE
241 #define CONFIG_BOOTP_BOOTPATH
242 #define CONFIG_BOOTP_GATEWAY
243 #define CONFIG_BOOTP_HOSTNAME
246 * Command line configuration.
248 #include <config_cmd_default.h>
250 #define CONFIG_CMD_ASKENV
251 #define CONFIG_CMD_BSP
252 #define CONFIG_CMD_DHCP
253 #define CONFIG_CMD_DIAG
254 #define CONFIG_CMD_EEPROM
255 #define CONFIG_CMD_ELF
256 #define CONFIG_CMD_FLASH
257 #define CONFIG_CMD_FAT
258 #define CONFIG_CMD_I2C
259 #define CONFIG_CMD_IMMAP
260 #define CONFIG_CMD_IRQ
261 #define CONFIG_CMD_MII
262 #define CONFIG_CMD_NET
263 #define CONFIG_CMD_NFS
264 #define CONFIG_CMD_PING
265 #define CONFIG_CMD_REGINFO
266 #define CONFIG_CMD_SDRAM
267 #define CONFIG_CMD_USB
269 #define CONFIG_SUPPORT_VFAT
271 /*-----------------------------------------------------------------------
272 * Miscellaneous configurable options
273 *----------------------------------------------------------------------*/
274 #define CFG_LONGHELP /* undef to save memory */
275 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
276 #if defined(CONFIG_CMD_KGDB)
277 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
279 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
281 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
282 #define CFG_MAXARGS 16 /* max number of command args */
283 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
285 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
286 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
288 #define CFG_LOAD_ADDR 0x100000 /* default load address */
289 #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
291 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
293 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
294 #define CONFIG_LOOPW 1 /* enable loopw command */
295 #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
296 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
297 #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
299 /*-----------------------------------------------------------------------
301 *----------------------------------------------------------------------*/
303 #define CONFIG_PCI /* include pci support */
304 #undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
305 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
306 #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
308 /* Board-specific PCI */
309 #define CFG_PCI_TARGET_INIT
310 #define CFG_PCI_MASTER_INIT
312 #define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
313 #define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
316 * For booting Linux, the board info and command line data
317 * have to be in the first 8 MB of memory, since this is
318 * the maximum mapped by the Linux kernel during initialization.
320 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
322 /*-----------------------------------------------------------------------
323 * External Bus Controller (EBC) Setup
324 *----------------------------------------------------------------------*/
325 #define CFG_FLASH CFG_FLASH_BASE
326 #define CFG_CS_1 0xC8000000 /* CAN */
327 #define CFG_CS_2 0xCC000000 /* CPLD and IMC-Bus Standard */
328 #define CFG_CPLD CFG_CS_2
329 #define CFG_CS_3 0xCD000000 /* CPLD and IMC-Bus Fast */
331 /*-----------------------------------------------------------------------
333 * Memory Bank 0 (BOOT-FLASH) initialization
335 #define CFG_BOOTFLASH_CS 0 /* Boot Flash chip connected to CSx */
336 #define CFG_EBC_PB0AP 0x02005400
337 #define CFG_EBC_PB0CR 0xFFF18000 /* (CFG_FLASH | 0xda000) */
338 #define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
339 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
340 #define CFG_MAX_FLASH_SECT 32 /* max number of sectors on one chip */
343 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
344 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
346 /* Memory Bank 1 CAN-Chips initialization */
347 #define CFG_EBC_PB1AP 0x02054500
348 #define CFG_EBC_PB1CR 0xC8018000
350 /* Memory Bank 2 CPLD/IMC-Bus standard initialization */
351 #define CFG_EBC_PB2AP 0x01840300
352 #define CFG_EBC_PB2CR 0xCC0BA000
354 /* Memory Bank 3 IMC-Bus fast mode initialization */
355 #define CFG_EBC_PB3AP 0x01800300
356 #define CFG_EBC_PB3CR 0xCE0BA000
358 /* Memory Bank 4 (not used) initialization */
362 /* Memory Bank 5 (not used) initialization */
366 #define HCU_CPLD_VERSION_REGISTER ( CFG_CPLD + 0x0F00000 )
367 #define HCU_HW_VERSION_REGISTER ( CFG_CPLD + 0x1400000 )
369 /*-----------------------------------------------------------------------
370 * Cache Configuration
371 *----------------------------------------------------------------------*/
372 #define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
373 #define CFG_CACHELINE_SIZE 32 /* ... */
374 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
377 * Internal Definitions
381 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
382 #define BOOTFLAG_WARM 0x02 /* Software reboot */
384 #define CFG_HUSH_PARSER /* use "hush" command parser */
385 #ifdef CFG_HUSH_PARSER
386 #define CFG_PROMPT_HUSH_PS2 "> "
389 #if defined(CONFIG_CMD_KGDB)
390 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
391 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
393 #endif /* __CONFIG_H */