2 * (C) Copyright 2007 Netstal Maschinen AG
3 * Niklaus Giger (Niklaus.Giger@netstal.com)
5 * (C) Copyright 2006-2007
6 * Stefan Roese, DENX Software Engineering, sr@denx.de.
9 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
10 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 /************************************************************************
29 * hcu5.h - configuration for HCU5 board (derived from sequoia.h)
30 ***********************************************************************/
35 /*-----------------------------------------------------------------------
36 * High Level Configuration Options
37 *----------------------------------------------------------------------*/
38 #define CONFIG_HCU5 1 /* Board is HCU5 */
39 #define CONFIG_440EPX 1 /* Specific PPC440EPx */
40 #define CONFIG_440 1 /* ... PPC440 family */
41 #define CONFIG_4xx 1 /* ... PPC4xx family */
42 #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
44 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
45 #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
47 /*-----------------------------------------------------------------------
48 * Base addresses -- Note these are effective addresses where the
49 * actual resources get mapped (not physical addresses)
50 *----------------------------------------------------------------------*/
51 #define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
52 #define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
54 #define CFG_BOOT_BASE_ADDR 0xfff00000
55 #define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
56 #define CFG_FLASH_BASE 0xfff80000 /* start of FLASH */
57 #define CFG_MONITOR_BASE TEXT_BASE
58 #define CFG_OCM_BASE 0xe0010000 /* ocm */
59 #define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */
60 #define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
61 #define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
62 #define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
63 #define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
65 /* Don't change either of these */
66 #define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
68 #define CFG_USB2D0_BASE 0xe0000100
69 #define CFG_USB_DEVICE 0xe0000000
70 #define CFG_USB_HOST 0xe0000400
72 /*-----------------------------------------------------------------------
73 * Initial RAM & stack pointer
74 *----------------------------------------------------------------------*/
75 /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
76 #define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
78 #define CFG_INIT_RAM_END (4 << 10)
79 #define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
80 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
81 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
83 /*-----------------------------------------------------------------------
85 *----------------------------------------------------------------------*/
86 #undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
87 #define CONFIG_BAUDRATE 9600
88 #undef CONFIG_SERIAL_MULTI /* needed to be able to define
89 CONFIG_SERIAL_SOFTWARE_FIFO, but
90 CONFIG_SERIAL_SOFTWARE_FIFO (16) does not work */
91 /* Size (bytes) of interrupt driven serial port buffer.
92 * Set to 0 to use polling instead of interrupts.
93 * Setting to 0 will also disable RTS/CTS handshaking.
95 #undef CONFIG_SERIAL_SOFTWARE_FIFO
96 #undef CONFIG_UART1_CONSOLE
98 #define CFG_BAUDRATE_TABLE \
99 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
101 /*-----------------------------------------------------------------------
103 *----------------------------------------------------------------------*/
105 #undef CFG_ENV_IS_IN_NVRAM
106 #undef CFG_ENV_IS_IN_FLASH
107 #define CFG_ENV_IS_IN_EEPROM
108 #undef CFG_ENV_IS_NOWHERE
110 #ifdef CFG_ENV_IS_IN_EEPROM
111 /* Put the environment after the SDRAM and bootstrap configuration */
112 #define PROM_SIZE 2048
113 #define CFG_BOOSTRAP_OPTION_OFFSET 512
114 #define CFG_ENV_OFFSET (CFG_BOOSTRAP_OPTION_OFFSET + 0x10)
115 #define CFG_ENV_SIZE (PROM_SIZE-CFG_ENV_OFFSET)
118 #ifdef CFG_ENV_IS_IN_FLASH
119 /* Put the environment in Flash */
120 #define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
121 #define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
122 #define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
124 /* Address and size of Redundant Environment Sector */
125 #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
126 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
129 /*-----------------------------------------------------------------------
131 *----------------------------------------------------------------------*/
132 #define CFG_MBYTES_SDRAM (128) /* 128 MB or 256 MB */
133 #define CFG_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */
134 #undef CONFIG_DDR_DATA_EYE /* Do not use DDR2 optimization */
135 #define CONFIG_DDR_ECC 1 /* enable ECC */
137 /*-----------------------------------------------------------------------
138 * I2C stuff for a ATMEL AT24C16 (2kB holding ENV, we are using the
139 * the second internal I2C controller of the PPC440EPx
140 *----------------------------------------------------------------------*/
141 #define CFG_SPD_BUS_NUM 1
143 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
144 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
145 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
146 #define CFG_I2C_SLAVE 0x7F
148 /* This is the 7bit address of the device, not including P. */
149 #define CFG_I2C_EEPROM_ADDR 0x50
150 #define CFG_I2C_EEPROM_ADDR_LEN 1
152 /* The EEPROM can do 16byte ( 1 << 4 ) page writes. */
153 #define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
154 #define CFG_EEPROM_PAGE_WRITE_BITS 4
155 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
156 #define CFG_EEPROM_PAGE_WRITE_ENABLE
157 #undef CFG_I2C_MULTI_EEPROMS
160 #define CONFIG_PREBOOT "echo;" \
161 "echo Type \"run nfs\" to mount Linux root filesystem over NFS;"\
164 #undef CONFIG_BOOTARGS
166 /* Setup some board specific values for the default environment variables */
167 #define CONFIG_HOSTNAME hcu5
168 #define CONFIG_IPADDR 172.25.1.42
169 #define CONFIG_ETHADDR 00:60:13:00:00:00 /* Netstal Machines AG MAC */
170 #define CONFIG_OVERWRITE_ETHADDR_ONCE
171 #define CONFIG_SERVERIP 172.25.1.3
173 #define CFG_TFTP_LOADADDR 0x01000000 /* @16 MB */
175 #define CONFIG_EXTRA_ENV_SETTINGS \
177 "loadaddr=0x01000000\0" \
178 "nfsargs=setenv bootargs root=/dev/nfs rw " \
179 "nfsroot=${serverip}:${rootpath}\0" \
180 "ramargs=setenv bootargs root=/dev/ram rw\0" \
181 "addip=setenv bootargs ${bootargs} " \
182 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
183 ":${hostname}:${netdev}:off panic=1\0" \
184 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
185 "nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
187 "bootfile=hcu5/uImage\0" \
188 "rootpath=/home/hcu/eldk/ppc_4xxFP\0" \
189 "load=tftp 100000 hcu5/u-boot.bin\0" \
190 "update=protect off FFFa0000 FFFFFFFF;era FFFa0000 FFFFFFFF;" \
191 "cp.b 100000 FFFa0000 60000\0" \
192 "upd=run load;run update\0" \
193 "vx=tftp ${loadaddr} hcu5/hcu5_vx_rom;" \
194 "setenv bootargs emac(0,0)hcu5_vx_rom e=${ipaddr} " \
195 " h=${serverip} u=dpu pw=netstal8752 tn=hcu5 f=0x3008;" \
196 "bootvx ${loadaddr}\0" \
198 #define CONFIG_BOOTCOMMAND "run vx"
201 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
203 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
206 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
207 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
209 #define CONFIG_M88E1111_PHY 1
210 #define CONFIG_IBM_EMAC4_V4 1
211 #define CONFIG_MII 1 /* MII PHY management */
212 #define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
214 #define CONFIG_PHY_RESET 1 /* reset phy upon startup */
216 #define CONFIG_HAS_ETH0
217 #define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
219 #define CONFIG_NET_MULTI 1
220 #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
221 #define CONFIG_PHY1_ADDR 1
224 #define CONFIG_USB_OHCI
225 #define CONFIG_USB_STORAGE
227 /* Comment this out to enable USB 1.1 device */
228 #define USB_2_0_DEVICE
231 #define CONFIG_MAC_PARTITION
232 #define CONFIG_DOS_PARTITION
233 #define CONFIG_ISO_PARTITION
238 #define CONFIG_BOOTP_BOOTFILESIZE
239 #define CONFIG_BOOTP_BOOTPATH
240 #define CONFIG_BOOTP_GATEWAY
241 #define CONFIG_BOOTP_HOSTNAME
244 * Command line configuration.
246 #include <config_cmd_default.h>
248 #define CONFIG_CMD_ASKENV
249 #define CONFIG_CMD_BSP
250 #define CONFIG_CMD_DHCP
251 #define CONFIG_CMD_DIAG
252 #define CONFIG_CMD_EEPROM
253 #define CONFIG_CMD_ELF
254 #define CONFIG_CMD_FLASH
255 #define CONFIG_CMD_FAT
256 #define CONFIG_CMD_I2C
257 #define CONFIG_CMD_IMMAP
258 #define CONFIG_CMD_IRQ
259 #define CONFIG_CMD_MII
260 #define CONFIG_CMD_NET
261 #define CONFIG_CMD_NFS
262 #define CONFIG_CMD_PING
263 #define CONFIG_CMD_REGINFO
264 #define CONFIG_CMD_SDRAM
265 #define CONFIG_CMD_USB
267 #define CONFIG_SUPPORT_VFAT
269 /*-----------------------------------------------------------------------
270 * Miscellaneous configurable options
271 *----------------------------------------------------------------------*/
272 #define CFG_LONGHELP /* undef to save memory */
273 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
274 #if defined(CONFIG_CMD_KGDB)
275 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
277 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
279 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
280 #define CFG_MAXARGS 16 /* max number of command args */
281 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
283 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
284 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
286 #define CFG_LOAD_ADDR 0x100000 /* default load address */
287 #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
289 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
291 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
292 #define CONFIG_LOOPW 1 /* enable loopw command */
293 #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
294 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
295 #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
297 /*-----------------------------------------------------------------------
299 *----------------------------------------------------------------------*/
301 #define CONFIG_PCI /* include pci support */
302 #undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
303 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
304 #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
306 /* Board-specific PCI */
307 #define CFG_PCI_TARGET_INIT
308 #define CFG_PCI_MASTER_INIT
310 #define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
311 #define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
314 * For booting Linux, the board info and command line data
315 * have to be in the first 8 MB of memory, since this is
316 * the maximum mapped by the Linux kernel during initialization.
318 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
320 /*-----------------------------------------------------------------------
321 * External Bus Controller (EBC) Setup
322 *----------------------------------------------------------------------*/
323 #define CFG_FLASH CFG_FLASH_BASE
324 #define CFG_CS_1 0xC8000000 /* CAN */
325 #define CFG_CS_2 0xCC000000 /* CPLD and IMC-Bus Standard */
326 #define CFG_CPLD CFG_CS_2
327 #define CFG_CS_3 0xCD000000 /* CPLD and IMC-Bus Fast */
329 /*-----------------------------------------------------------------------
331 * Memory Bank 0 (BOOT-FLASH) initialization
333 #define CFG_BOOTFLASH_CS 0 /* Boot Flash chip connected to CSx */
334 #define CFG_EBC_PB0AP 0x02005400
335 #define CFG_EBC_PB0CR 0xFFF18000 /* (CFG_FLASH | 0xda000) */
336 #define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
337 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
338 #define CFG_MAX_FLASH_SECT 32 /* max number of sectors on one chip */
341 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
342 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
344 /* Memory Bank 1 CAN-Chips initialization */
345 #define CFG_EBC_PB1AP 0x02054500
346 #define CFG_EBC_PB1CR 0xC8018000
348 /* Memory Bank 2 CPLD/IMC-Bus standard initialization */
349 #define CFG_EBC_PB2AP 0x01840300
350 #define CFG_EBC_PB2CR 0xCC0BA000
352 /* Memory Bank 3 IMC-Bus fast mode initialization */
353 #define CFG_EBC_PB3AP 0x01800300
354 #define CFG_EBC_PB3CR 0xCE0BA000
356 /* Memory Bank 4 (not used) initialization */
360 /* Memory Bank 5 (not used) initialization */
364 #define HCU_CPLD_VERSION_REGISTER ( CFG_CPLD + 0x0F00000 )
365 #define HCU_HW_VERSION_REGISTER ( CFG_CPLD + 0x1400000 )
367 /*-----------------------------------------------------------------------
368 * Cache Configuration
369 *----------------------------------------------------------------------*/
370 #define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
371 #define CFG_CACHELINE_SIZE 32 /* ... */
372 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
375 * Internal Definitions
379 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
380 #define BOOTFLAG_WARM 0x02 /* Software reboot */
382 #define CFG_HUSH_PARSER /* use "hush" command parser */
383 #ifdef CFG_HUSH_PARSER
384 #define CFG_PROMPT_HUSH_PS2 "> "
387 #if defined(CONFIG_CMD_KGDB)
388 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
389 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
391 #endif /* __CONFIG_H */