include/configs/ge_bx50v3.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2015 Timesys Corporation
   4  * Copyright (C) 2015 General Electric Company
   5  * Copyright (C) 2014 Advantech
   6  * Copyright (C) 2012 Freescale Semiconductor, Inc.
   7  *
   8  * Configuration settings for the GE MX6Q Bx50v3 boards.
   9  */
  10
  11 #ifndef __GE_BX50V3_CONFIG_H
  12 #define __GE_BX50V3_CONFIG_H
  13
  14 #include <asm/arch/imx-regs.h>
  15 #include <asm/mach-imx/gpio.h>
  16
  17 #define CONFIG_BOARD_NAME       "General Electric Bx50v3"
  18
  19 #define CONFIG_MXC_UART_BASE    UART3_BASE
  20 #define CONSOLE_DEV     "ttymxc2"
  21
  22 #define CONFIG_SUPPORT_EMMC_BOOT
  23
  24
  25 #include "mx6_common.h"
  26 #include <linux/sizes.h>
  27
  28 #define CONFIG_CMDLINE_TAG
  29 #define CONFIG_SETUP_MEMORY_TAGS
  30 #define CONFIG_INITRD_TAG
  31 #define CONFIG_REVISION_TAG
  32 #define CONFIG_SYS_MALLOC_LEN           (10 * SZ_1M)
  33
  34 #define CONFIG_WATCHDOG_TIMEOUT_MSECS 6000
  35
  36 #define CONFIG_MXC_UART
  37
  38 #define CONFIG_MXC_OCOTP
  39
  40 /* SATA Configs */
  41 #ifdef CONFIG_CMD_SATA
  42 #define CONFIG_SYS_SATA_MAX_DEVICE      1
  43 #define CONFIG_DWC_AHSATA_PORT_ID       0
  44 #define CONFIG_DWC_AHSATA_BASE_ADDR     SATA_ARB_BASE_ADDR
  45 #define CONFIG_LBA48
  46 #endif
  47
  48 /* MMC Configs */
  49 #define CONFIG_FSL_USDHC
  50 #define CONFIG_SYS_FSL_ESDHC_ADDR      0
  51
  52 /* USB Configs */
  53 #ifdef CONFIG_USB
  54 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  55 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  56 #define CONFIG_MXC_USB_PORTSC   (PORT_PTS_UTMI | PORT_PTS_PTW)
  57 #define CONFIG_MXC_USB_FLAGS    0
  58
  59 #define CONFIG_USBD_HS
  60 #define CONFIG_USB_GADGET_MASS_STORAGE
  61 #endif
  62
  63 /* Networking Configs */
  64 #ifdef CONFIG_NET
  65 #define CONFIG_FEC_MXC
  66 #define IMX_FEC_BASE                    ENET_BASE_ADDR
  67 #define CONFIG_FEC_XCV_TYPE             RGMII
  68 #define CONFIG_ETHPRIME         "FEC"
  69 #define CONFIG_FEC_MXC_PHYADDR          4
  70 #define CONFIG_PHY_ATHEROS
  71 #endif
  72
  73 /* Serial Flash */
  74
  75 /* allow to overwrite serial and ethaddr */
  76 #define CONFIG_ENV_OVERWRITE
  77
  78 #define CONFIG_LOADADDR 0x12000000
  79
  80 #define CONFIG_EXTRA_ENV_SETTINGS \
  81         "bootcause=POR\0" \
  82         "image=/boot/fitImage\0" \
  83         "fdt_high=0xffffffff\0" \
  84         "dev=mmc\0" \
  85         "devnum=1\0" \
  86         "rootdev=mmcblk0p\0" \
  87         "quiet=quiet loglevel=0\0" \
  88         "console=" CONSOLE_DEV "\0" \
  89         "setargs=setenv bootargs root=/dev/${rootdev}${partnum} " \
  90                 "ro rootwait cma=128M " \
  91                 "bootcause=${bootcause} " \
  92                 "${quiet} console=${console} ${rtc_status} " \
  93                 "${videoargs}" "\0" \
  94         "doquiet=" \
  95                 "if ext2load ${dev} ${devnum}:5 0x7000A000 /boot/console; " \
  96                         "then setenv quiet; fi\0" \
  97         "hasfirstboot=" \
  98                 "ext2load ${dev} ${devnum}:${partnum} 0x7000A000 " \
  99                 "/boot/bootcause/firstboot\0" \
 100         "swappartitions=" \
 101                 "setexpr partnum 3 - ${partnum}\0" \
 102         "failbootcmd=" \
 103                 "bx50_backlight_enable; " \
 104                 "msg=\"Monitor failed to start.  Try again, or contact GE Service for support.\"; " \
 105                 "echo $msg; " \
 106                 "setenv stdout vga; " \
 107                 "echo \"\n\n\n\n    \" $msg; " \
 108                 "setenv stdout serial; " \
 109                 "mw.b 0x7000A000 0xbc; " \
 110                 "mw.b 0x7000A001 0x00; " \
 111                 "ext4write ${dev} ${devnum}:5 0x7000A000 /boot/failures 2\0" \
 112         "altbootcmd=" \
 113                 "run doquiet; " \
 114                 "setenv partnum 1; run hasfirstboot || setenv partnum 2; " \
 115                 "run hasfirstboot || setenv partnum 0; " \
 116                 "if test ${partnum} != 0; then " \
 117                         "setenv bootcause REVERT; " \
 118                         "run swappartitions loadimage doboot; " \
 119                 "fi; " \
 120                 "run failbootcmd\0" \
 121         "loadimage=" \
 122                 "ext2load ${dev} ${devnum}:${partnum} ${loadaddr} ${image}\0" \
 123         "doboot=" \
 124                 "echo Booting from ${dev}:${devnum}:${partnum} ...; " \
 125                 "run setargs; " \
 126                 "bootm ${loadaddr}#conf@${confidx}\0" \
 127         "tryboot=" \
 128                 "setenv partnum 1; run hasfirstboot || setenv partnum 2; " \
 129                 "run loadimage || run swappartitions && run loadimage || " \
 130                 "setenv partnum 0 && echo MISSING IMAGE;" \
 131                 "run doboot; " \
 132                 "run failbootcmd\0" \
 133
 134 #define CONFIG_MMCBOOTCOMMAND \
 135         "if mmc dev ${devnum}; then " \
 136                 "run doquiet; " \
 137                 "run tryboot; " \
 138         "fi; " \
 139
 140 #define CONFIG_USBBOOTCOMMAND \
 141         "echo Unsupported; " \
 142
 143 #ifdef CONFIG_CMD_USB
 144 #define CONFIG_BOOTCOMMAND CONFIG_USBBOOTCOMMAND
 145 #else
 146 #define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
 147 #endif
 148
 149 #define CONFIG_ARP_TIMEOUT     200UL
 150
 151 /* Miscellaneous configurable options */
 152
 153 #define CONFIG_SYS_MEMTEST_START       0x10000000
 154 #define CONFIG_SYS_MEMTEST_END         0x10010000
 155 #define CONFIG_SYS_MEMTEST_SCRATCH     0x10800000
 156
 157 #define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR
 158
 159 /* Physical Memory Map */
 160 #define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
 161
 162 #define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
 163 #define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
 164 #define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
 165
 166 #define CONFIG_SYS_INIT_SP_OFFSET \
 167         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 168 #define CONFIG_SYS_INIT_SP_ADDR \
 169         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 170
 171 /* environment organization */
 172 #define CONFIG_ENV_SIZE         (8 * 1024)
 173 #define CONFIG_ENV_OFFSET               (768 * 1024)
 174 #define CONFIG_ENV_SECT_SIZE            (64 * 1024)
 175
 176 #define CONFIG_SYS_FSL_USDHC_NUM        3
 177
 178 /* Framebuffer */
 179 #define CONFIG_VIDEO
 180 #ifdef CONFIG_VIDEO
 181 #define CONFIG_VIDEO_IPUV3
 182 #define CONFIG_CFB_CONSOLE
 183 #define CONFIG_VGA_AS_SINGLE_DEVICE
 184 #define CONFIG_SYS_CONSOLE_FG_COL 0xFF
 185 #define CONFIG_SYS_CONSOLE_BG_COL 0x00
 186 #define CONFIG_HIDE_LOGO_VERSION
 187 #define CONFIG_IMX_HDMI
 188 #define CONFIG_IMX_VIDEO_SKIP
 189 #define CONFIG_CMD_BMP
 190 #endif
 191
 192 #define CONFIG_PWM_IMX
 193 #define CONFIG_IMX6_PWM_PER_CLK 66000000
 194
 195 #define CONFIG_PCI
 196 #define CONFIG_PCI_PNP
 197 #define CONFIG_PCI_SCAN_SHOW
 198 #define CONFIG_PCIE_IMX
 199 #define CONFIG_PCIE_IMX_PERST_GPIO      IMX_GPIO_NR(7, 12)
 200 #define CONFIG_PCIE_IMX_POWER_GPIO      IMX_GPIO_NR(1, 5)
 201
 202 #define CONFIG_RTC_RX8010SJ
 203 #define CONFIG_SYS_RTC_BUS_NUM 2
 204 #define CONFIG_SYS_I2C_RTC_ADDR 0x32
 205
 206 /* I2C Configs */
 207 #define CONFIG_SYS_I2C
 208 #define CONFIG_SYS_I2C_MXC
 209 #define CONFIG_SYS_I2C_SPEED              100000
 210 #define CONFIG_SYS_I2C_MXC_I2C1
 211 #define CONFIG_SYS_I2C_MXC_I2C2
 212 #define CONFIG_SYS_I2C_MXC_I2C3
 213
 214 #define CONFIG_SYS_NUM_I2C_BUSES        11
 215 #define CONFIG_SYS_I2C_MAX_HOPS         1
 216 #define CONFIG_SYS_I2C_BUSES    {       {0, {I2C_NULL_HOP} }, \
 217                                         {1, {I2C_NULL_HOP} }, \
 218                                         {2, {I2C_NULL_HOP} }, \
 219                                         {0, {{I2C_MUX_PCA9547, 0x70, 0} } }, \
 220                                         {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
 221                                         {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
 222                                         {0, {{I2C_MUX_PCA9547, 0x70, 3} } }, \
 223                                         {0, {{I2C_MUX_PCA9547, 0x70, 4} } }, \
 224                                         {0, {{I2C_MUX_PCA9547, 0x70, 5} } }, \
 225                                         {0, {{I2C_MUX_PCA9547, 0x70, 6} } }, \
 226                                         {0, {{I2C_MUX_PCA9547, 0x70, 7} } }, \
 227                                 }
 228
 229 #define CONFIG_BCH
 230
 231 #endif  /* __GE_BX50V3_CONFIG_H */