1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2015 Timesys Corporation
4 * Copyright (C) 2015 General Electric Company
5 * Copyright (C) 2014 Advantech
6 * Copyright (C) 2012 Freescale Semiconductor, Inc.
8 * Configuration settings for the GE MX6Q Bx50v3 boards.
11 #ifndef __GE_BX50V3_CONFIG_H
12 #define __GE_BX50V3_CONFIG_H
14 #include <asm/arch/imx-regs.h>
15 #include <asm/mach-imx/gpio.h>
17 #if defined(CONFIG_TARGET_GE_B450V3)
18 #define CONFIG_BOARD_NAME "General Electric B450v3"
19 #elif defined(CONFIG_TARGET_GE_B650V3)
20 #define CONFIG_BOARD_NAME "General Electric B650v3"
21 #elif defined(CONFIG_TARGET_GE_B850V3)
22 #define CONFIG_BOARD_NAME "General Electric B850v3"
23 #undef BX50V3_BOOTARGS_EXTRA
25 #define CONFIG_BOARD_NAME "General Electric BA16 Generic"
28 #define CONFIG_MXC_UART_BASE UART3_BASE
29 #define CONSOLE_DEV "ttymxc2"
31 #define CONFIG_SUPPORT_EMMC_BOOT
34 #include "mx6_common.h"
35 #include <linux/sizes.h>
37 #define CONFIG_CMDLINE_TAG
38 #define CONFIG_SETUP_MEMORY_TAGS
39 #define CONFIG_INITRD_TAG
40 #define CONFIG_REVISION_TAG
41 #define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
43 #define CONFIG_HW_WATCHDOG
44 #define CONFIG_IMX_WATCHDOG
45 #define CONFIG_WATCHDOG_TIMEOUT_MSECS 6000
47 #define CONFIG_MXC_UART
49 #define CONFIG_MXC_OCOTP
52 #ifdef CONFIG_CMD_SATA
53 #define CONFIG_SYS_SATA_MAX_DEVICE 1
54 #define CONFIG_DWC_AHSATA_PORT_ID 0
55 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
60 #define CONFIG_FSL_USDHC
61 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
62 #define CONFIG_BOUNCE_BUFFER
66 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
67 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
68 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
69 #define CONFIG_MXC_USB_FLAGS 0
71 #define CONFIG_USBD_HS
72 #define CONFIG_USB_GADGET_MASS_STORAGE
75 /* Networking Configs */
77 #define CONFIG_FEC_MXC
79 #define IMX_FEC_BASE ENET_BASE_ADDR
80 #define CONFIG_FEC_XCV_TYPE RGMII
81 #define CONFIG_ETHPRIME "FEC"
82 #define CONFIG_FEC_MXC_PHYADDR 4
83 #define CONFIG_PHY_ATHEROS
88 #define CONFIG_SF_DEFAULT_BUS 0
89 #define CONFIG_SF_DEFAULT_CS 0
90 #define CONFIG_SF_DEFAULT_SPEED 20000000
91 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
94 /* allow to overwrite serial and ethaddr */
95 #define CONFIG_ENV_OVERWRITE
97 #define CONFIG_LOADADDR 0x12000000
99 #define CONFIG_EXTRA_ENV_SETTINGS \
102 "image=/boot/fitImage\0" \
103 "fdt_high=0xffffffff\0" \
106 "rootdev=mmcblk0p\0" \
107 "quiet=quiet loglevel=0\0" \
108 "console=" CONSOLE_DEV "\0" \
109 "setargs=setenv bootargs root=/dev/${rootdev}${partnum} " \
110 "ro rootwait cma=128M " \
111 "bootcause=${bootcause} " \
112 "${quiet} console=${console} ${rtc_status} " \
113 "${videoargs}" "\0" \
115 "if ext2load ${dev} ${devnum}:5 0x7000A000 /boot/console; " \
116 "then setenv quiet; fi\0" \
118 "ext2load ${dev} ${devnum}:${partnum} 0x7000A000 " \
119 "/boot/bootcause/firstboot\0" \
121 "setexpr partnum 3 - ${partnum}\0" \
123 "bx50_backlight_enable; " \
124 "msg=\"Monitor failed to start. Try again, or contact GE Service for support.\"; " \
126 "setenv stdout vga; " \
127 "echo \"\n\n\n\n \" $msg; " \
128 "setenv stdout serial; " \
129 "mw.b 0x7000A000 0xbc; " \
130 "mw.b 0x7000A001 0x00; " \
131 "ext4write ${dev} ${devnum}:5 0x7000A000 /boot/failures 2\0" \
134 "setenv partnum 1; run hasfirstboot || setenv partnum 2; " \
135 "run hasfirstboot || setenv partnum 0; " \
136 "if test ${partnum} != 0; then " \
137 "setenv bootcause REVERT; " \
138 "run swappartitions loadimage doboot; " \
140 "run failbootcmd\0" \
142 "ext2load ${dev} ${devnum}:${partnum} ${loadaddr} ${image}\0" \
144 "echo Booting from ${dev}:${devnum}:${partnum} ...; " \
146 "bootm ${loadaddr}#conf@${confidx}\0" \
148 "setenv partnum 1; run hasfirstboot || setenv partnum 2; " \
149 "run loadimage || run swappartitions && run loadimage || " \
150 "setenv partnum 0 && echo MISSING IMAGE;" \
152 "run failbootcmd\0" \
154 #define CONFIG_MMCBOOTCOMMAND \
155 "if mmc dev ${devnum}; then " \
160 #define CONFIG_USBBOOTCOMMAND \
161 "echo Unsupported; " \
163 #ifdef CONFIG_CMD_USB
164 #define CONFIG_BOOTCOMMAND CONFIG_USBBOOTCOMMAND
166 #define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
169 #define CONFIG_ARP_TIMEOUT 200UL
171 /* Miscellaneous configurable options */
173 #define CONFIG_SYS_MEMTEST_START 0x10000000
174 #define CONFIG_SYS_MEMTEST_END 0x10010000
175 #define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
177 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
179 /* Physical Memory Map */
180 #define CONFIG_NR_DRAM_BANKS 1
181 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
183 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
184 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
185 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
187 #define CONFIG_SYS_INIT_SP_OFFSET \
188 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
189 #define CONFIG_SYS_INIT_SP_ADDR \
190 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
192 /* environment organization */
193 #define CONFIG_ENV_SIZE (8 * 1024)
194 #define CONFIG_ENV_OFFSET (768 * 1024)
195 #define CONFIG_ENV_SECT_SIZE (64 * 1024)
196 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
197 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
198 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
199 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
201 #ifndef CONFIG_SYS_DCACHE_OFF
204 #define CONFIG_SYS_FSL_USDHC_NUM 3
209 #define CONFIG_VIDEO_IPUV3
210 #define CONFIG_CFB_CONSOLE
211 #define CONFIG_VGA_AS_SINGLE_DEVICE
212 #define CONFIG_SYS_CONSOLE_FG_COL 0xFF
213 #define CONFIG_SYS_CONSOLE_BG_COL 0x00
214 #define CONFIG_HIDE_LOGO_VERSION
215 #define CONFIG_IMX_HDMI
216 #define CONFIG_IMX_VIDEO_SKIP
217 #define CONFIG_CMD_BMP
220 #define CONFIG_PWM_IMX
221 #define CONFIG_IMX6_PWM_PER_CLK 66000000
224 #define CONFIG_PCI_PNP
225 #define CONFIG_PCI_SCAN_SHOW
226 #define CONFIG_PCIE_IMX
227 #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12)
228 #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(1, 5)
230 #define CONFIG_RTC_RX8010SJ
231 #define CONFIG_SYS_RTC_BUS_NUM 2
232 #define CONFIG_SYS_I2C_RTC_ADDR 0x32
235 #define CONFIG_SYS_I2C
236 #define CONFIG_SYS_I2C_MXC
237 #define CONFIG_SYS_I2C_SPEED 100000
238 #define CONFIG_SYS_I2C_MXC_I2C1
239 #define CONFIG_SYS_I2C_MXC_I2C2
240 #define CONFIG_SYS_I2C_MXC_I2C3
242 #define CONFIG_SYS_NUM_I2C_BUSES 11
243 #define CONFIG_SYS_I2C_MAX_HOPS 1
244 #define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \
245 {1, {I2C_NULL_HOP} }, \
246 {2, {I2C_NULL_HOP} }, \
247 {0, {{I2C_MUX_PCA9547, 0x70, 0} } }, \
248 {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
249 {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
250 {0, {{I2C_MUX_PCA9547, 0x70, 3} } }, \
251 {0, {{I2C_MUX_PCA9547, 0x70, 4} } }, \
252 {0, {{I2C_MUX_PCA9547, 0x70, 5} } }, \
253 {0, {{I2C_MUX_PCA9547, 0x70, 6} } }, \
254 {0, {{I2C_MUX_PCA9547, 0x70, 7} } }, \
259 #endif /* __GE_BX50V3_CONFIG_H */