1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2015 Timesys Corporation
4 * Copyright (C) 2015 General Electric Company
5 * Copyright (C) 2014 Advantech
6 * Copyright (C) 2012 Freescale Semiconductor, Inc.
8 * Configuration settings for the GE MX6Q Bx50v3 boards.
11 #ifndef __GE_BX50V3_CONFIG_H
12 #define __GE_BX50V3_CONFIG_H
14 #include <asm/arch/imx-regs.h>
15 #include <asm/mach-imx/gpio.h>
17 #define CONFIG_BOARD_NAME "General Electric Bx50v3"
19 #define CONFIG_MXC_UART_BASE UART3_BASE
20 #define CONSOLE_DEV "ttymxc2"
22 #define CONFIG_SUPPORT_EMMC_BOOT
25 #include "mx6_common.h"
26 #include <linux/sizes.h>
28 #define CONFIG_CMDLINE_TAG
29 #define CONFIG_SETUP_MEMORY_TAGS
30 #define CONFIG_INITRD_TAG
31 #define CONFIG_REVISION_TAG
32 #define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
34 #define CONFIG_WATCHDOG_TIMEOUT_MSECS 6000
36 #define CONFIG_MXC_UART
38 #define CONFIG_MXC_OCOTP
41 #ifdef CONFIG_CMD_SATA
42 #define CONFIG_SYS_SATA_MAX_DEVICE 1
43 #define CONFIG_DWC_AHSATA_PORT_ID 0
44 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
50 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
51 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
52 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
53 #define CONFIG_MXC_USB_FLAGS 0
55 #define CONFIG_USBD_HS
56 #define CONFIG_USB_GADGET_MASS_STORAGE
59 /* Networking Configs */
61 #define CONFIG_FEC_MXC
62 #define IMX_FEC_BASE ENET_BASE_ADDR
63 #define CONFIG_FEC_XCV_TYPE RGMII
64 #define CONFIG_ETHPRIME "FEC"
65 #define CONFIG_FEC_MXC_PHYADDR 4
66 #define CONFIG_PHY_ATHEROS
71 /* allow to overwrite serial and ethaddr */
72 #define CONFIG_ENV_OVERWRITE
74 #define CONFIG_LOADADDR 0x12000000
76 #define CONFIG_EXTRA_ENV_SETTINGS \
78 "image=/boot/fitImage\0" \
79 "fdt_high=0xffffffff\0" \
82 "rootdev=mmcblk0p\0" \
83 "quiet=quiet loglevel=0\0" \
84 "console=" CONSOLE_DEV "\0" \
85 "setargs=setenv bootargs root=/dev/${rootdev}${partnum} " \
86 "ro rootwait cma=128M " \
87 "bootcause=${bootcause} " \
88 "${quiet} console=${console} ${rtc_status} " \
91 "if ext2load ${dev} ${devnum}:5 0x7000A000 /boot/console; " \
92 "then setenv quiet; fi\0" \
94 "ext2load ${dev} ${devnum}:${partnum} 0x7000A000 " \
95 "/boot/bootcause/firstboot\0" \
97 "setexpr partnum 3 - ${partnum}\0" \
99 "bx50_backlight_enable; " \
100 "msg=\"Monitor failed to start. Try again, or contact GE Service for support.\"; " \
102 "setenv stdout vga; " \
103 "echo \"\n\n\n\n \" $msg; " \
104 "setenv stdout serial; " \
105 "mw.b 0x7000A000 0xbc; " \
106 "mw.b 0x7000A001 0x00; " \
107 "ext4write ${dev} ${devnum}:5 0x7000A000 /boot/failures 2\0" \
110 "setenv partnum 1; run hasfirstboot || setenv partnum 2; " \
111 "run hasfirstboot || setenv partnum 0; " \
112 "if test ${partnum} != 0; then " \
113 "setenv bootcause REVERT; " \
114 "run swappartitions loadimage doboot; " \
116 "run failbootcmd\0" \
118 "ext2load ${dev} ${devnum}:${partnum} ${loadaddr} ${image}\0" \
120 "echo Booting from ${dev}:${devnum}:${partnum} ...; " \
122 "bootm ${loadaddr}#conf@${confidx}\0" \
124 "setenv partnum 1; run hasfirstboot || setenv partnum 2; " \
125 "run loadimage || run swappartitions && run loadimage || " \
126 "setenv partnum 0 && echo MISSING IMAGE;" \
128 "run failbootcmd\0" \
130 #define CONFIG_MMCBOOTCOMMAND \
131 "if mmc dev ${devnum}; then " \
136 #define CONFIG_USBBOOTCOMMAND \
137 "echo Unsupported; " \
139 #ifdef CONFIG_CMD_USB
140 #define CONFIG_BOOTCOMMAND CONFIG_USBBOOTCOMMAND
142 #define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
145 #define CONFIG_ARP_TIMEOUT 200UL
147 /* Miscellaneous configurable options */
149 #define CONFIG_SYS_MEMTEST_START 0x10000000
150 #define CONFIG_SYS_MEMTEST_END 0x10010000
151 #define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
153 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
155 /* Physical Memory Map */
156 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
158 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
159 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
160 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
162 #define CONFIG_SYS_INIT_SP_OFFSET \
163 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
164 #define CONFIG_SYS_INIT_SP_ADDR \
165 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
167 /* environment organization */
168 #define CONFIG_ENV_SIZE (8 * 1024)
169 #define CONFIG_ENV_OFFSET (768 * 1024)
170 #define CONFIG_ENV_SECT_SIZE (64 * 1024)
172 #define CONFIG_SYS_FSL_USDHC_NUM 3
177 #define CONFIG_VIDEO_IPUV3
178 #define CONFIG_CFB_CONSOLE
179 #define CONFIG_VGA_AS_SINGLE_DEVICE
180 #define CONFIG_SYS_CONSOLE_FG_COL 0xFF
181 #define CONFIG_SYS_CONSOLE_BG_COL 0x00
182 #define CONFIG_HIDE_LOGO_VERSION
183 #define CONFIG_IMX_HDMI
184 #define CONFIG_IMX_VIDEO_SKIP
185 #define CONFIG_CMD_BMP
188 #define CONFIG_PWM_IMX
189 #define CONFIG_IMX6_PWM_PER_CLK 66000000
192 #define CONFIG_PCI_PNP
193 #define CONFIG_PCI_SCAN_SHOW
194 #define CONFIG_PCIE_IMX
195 #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12)
196 #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(1, 5)
198 #define CONFIG_RTC_RX8010SJ
199 #define CONFIG_SYS_RTC_BUS_NUM 2
200 #define CONFIG_SYS_I2C_RTC_ADDR 0x32
203 #define CONFIG_SYS_I2C
204 #define CONFIG_SYS_I2C_MXC
205 #define CONFIG_SYS_I2C_SPEED 100000
206 #define CONFIG_SYS_I2C_MXC_I2C1
207 #define CONFIG_SYS_I2C_MXC_I2C2
208 #define CONFIG_SYS_I2C_MXC_I2C3
210 #define CONFIG_SYS_NUM_I2C_BUSES 11
211 #define CONFIG_SYS_I2C_MAX_HOPS 1
212 #define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \
213 {1, {I2C_NULL_HOP} }, \
214 {2, {I2C_NULL_HOP} }, \
215 {0, {{I2C_MUX_PCA9547, 0x70, 0} } }, \
216 {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
217 {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
218 {0, {{I2C_MUX_PCA9547, 0x70, 3} } }, \
219 {0, {{I2C_MUX_PCA9547, 0x70, 4} } }, \
220 {0, {{I2C_MUX_PCA9547, 0x70, 5} } }, \
221 {0, {{I2C_MUX_PCA9547, 0x70, 6} } }, \
222 {0, {{I2C_MUX_PCA9547, 0x70, 7} } }, \
227 #endif /* __GE_BX50V3_CONFIG_H */