2 * Copyright (C) 2015 Timesys Corporation
3 * Copyright (C) 2015 General Electric Company
4 * Copyright (C) 2014 Advantech
5 * Copyright (C) 2012 Freescale Semiconductor, Inc.
7 * Configuration settings for the GE MX6Q Bx50v3 boards.
9 * SPDX-License-Identifier: GPL-2.0+
12 #ifndef __GE_BX50V3_CONFIG_H
13 #define __GE_BX50V3_CONFIG_H
15 #include <asm/arch/imx-regs.h>
16 #include <asm/mach-imx/gpio.h>
18 #define BX50V3_BOOTARGS_EXTRA
19 #if defined(CONFIG_TARGET_GE_B450V3)
20 #define CONFIG_BOARD_NAME "General Electric B450v3"
21 #elif defined(CONFIG_TARGET_GE_B650V3)
22 #define CONFIG_BOARD_NAME "General Electric B650v3"
23 #elif defined(CONFIG_TARGET_GE_B850V3)
24 #define CONFIG_BOARD_NAME "General Electric B850v3"
25 #undef BX50V3_BOOTARGS_EXTRA
26 #define BX50V3_BOOTARGS_EXTRA "video=DP-1:1024x768@60 " \
27 "video=HDMI-A-1:1024x768@60 "
29 #define CONFIG_BOARD_NAME "General Electric BA16 Generic"
32 #define CONFIG_MXC_UART_BASE UART3_BASE
33 #define CONSOLE_DEV "ttymxc2"
35 #define CONFIG_SUPPORT_EMMC_BOOT
38 #include "mx6_common.h"
39 #include <linux/sizes.h>
41 #define CONFIG_CMDLINE_TAG
42 #define CONFIG_SETUP_MEMORY_TAGS
43 #define CONFIG_INITRD_TAG
44 #define CONFIG_REVISION_TAG
45 #define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
47 #define CONFIG_HW_WATCHDOG
48 #define CONFIG_IMX_WATCHDOG
49 #define CONFIG_WATCHDOG_TIMEOUT_MSECS 6000
51 #define CONFIG_LAST_STAGE_INIT
53 #define CONFIG_MXC_UART
55 #define CONFIG_MXC_OCOTP
58 #ifdef CONFIG_CMD_SATA
59 #define CONFIG_SYS_SATA_MAX_DEVICE 1
60 #define CONFIG_DWC_AHSATA_PORT_ID 0
61 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
66 #define CONFIG_FSL_ESDHC
67 #define CONFIG_FSL_USDHC
68 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
69 #define CONFIG_BOUNCE_BUFFER
73 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
74 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
75 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
76 #define CONFIG_MXC_USB_FLAGS 0
78 #define CONFIG_USBD_HS
79 #define CONFIG_USB_GADGET_MASS_STORAGE
82 /* Networking Configs */
84 #define CONFIG_FEC_MXC
86 #define IMX_FEC_BASE ENET_BASE_ADDR
87 #define CONFIG_FEC_XCV_TYPE RGMII
88 #define CONFIG_ETHPRIME "FEC"
89 #define CONFIG_FEC_MXC_PHYADDR 4
90 #define CONFIG_PHY_ATHEROS
95 #define CONFIG_SF_DEFAULT_BUS 0
96 #define CONFIG_SF_DEFAULT_CS 0
97 #define CONFIG_SF_DEFAULT_SPEED 20000000
98 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
101 /* allow to overwrite serial and ethaddr */
102 #define CONFIG_ENV_OVERWRITE
103 #define CONFIG_CONS_INDEX 1
105 #define CONFIG_LOADADDR 0x12000000
107 #define CONFIG_EXTRA_ENV_SETTINGS \
110 "image=/boot/fitImage\0" \
111 "fdt_high=0xffffffff\0" \
114 "rootdev=mmcblk0p\0" \
115 "quiet=quiet loglevel=0\0" \
116 "console=" CONSOLE_DEV "\0" \
117 "setargs=setenv bootargs root=/dev/${rootdev}${partnum} " \
118 "ro rootwait cma=128M " \
119 "bootcause=${bootcause} " \
120 "${quiet} console=${console} ${rtc_status} " \
121 BX50V3_BOOTARGS_EXTRA "\0" \
123 "if ext2load ${dev} ${devnum}:5 0x7000A000 /boot/console; " \
124 "then setenv quiet; fi\0" \
126 "ext2load ${dev} ${devnum}:${partnum} 0x7000A000 " \
127 "/boot/bootcause/firstboot\0" \
129 "setexpr partnum 3 - ${partnum}\0" \
131 "bx50_backlight_enable; " \
132 "msg=\"Monitor failed to start. Try again, or contact GE Service for support.\"; " \
134 "setenv stdout vga; " \
135 "echo \"\n\n\n\n \" $msg; " \
136 "setenv stdout serial; " \
137 "mw.b 0x7000A000 0xbc; " \
138 "mw.b 0x7000A001 0x00; " \
139 "ext4write ${dev} ${devnum}:5 0x7000A000 /boot/failures 2\0" \
142 "setenv partnum 1; run hasfirstboot || setenv partnum 2; " \
143 "run hasfirstboot || setenv partnum 0; " \
144 "if test ${partnum} != 0; then " \
145 "setenv bootcause REVERT; " \
146 "run swappartitions loadimage doboot; " \
148 "run failbootcmd\0" \
150 "ext2load ${dev} ${devnum}:${partnum} ${loadaddr} ${image}\0" \
152 "echo Booting from ${dev}:${devnum}:${partnum} ...; " \
154 "bootm ${loadaddr}#conf@${confidx}\0" \
156 "setenv partnum 1; run hasfirstboot || setenv partnum 2; " \
157 "run loadimage || run swappartitions && run loadimage || " \
158 "setenv partnum 0 && echo MISSING IMAGE;" \
160 "run failbootcmd\0" \
162 #define CONFIG_MMCBOOTCOMMAND \
163 "if mmc dev ${devnum}; then " \
168 #define CONFIG_USBBOOTCOMMAND \
169 "echo Unsupported; " \
171 #ifdef CONFIG_CMD_USB
172 #define CONFIG_BOOTCOMMAND CONFIG_USBBOOTCOMMAND
174 #define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
177 #define CONFIG_ARP_TIMEOUT 200UL
179 /* Miscellaneous configurable options */
181 #define CONFIG_SYS_MEMTEST_START 0x10000000
182 #define CONFIG_SYS_MEMTEST_END 0x10010000
183 #define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
185 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
187 /* Physical Memory Map */
188 #define CONFIG_NR_DRAM_BANKS 1
189 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
191 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
192 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
193 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
195 #define CONFIG_SYS_INIT_SP_OFFSET \
196 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
197 #define CONFIG_SYS_INIT_SP_ADDR \
198 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
200 /* environment organization */
201 #define CONFIG_ENV_SIZE (8 * 1024)
202 #define CONFIG_ENV_OFFSET (768 * 1024)
203 #define CONFIG_ENV_SECT_SIZE (64 * 1024)
204 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
205 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
206 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
207 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
209 #ifndef CONFIG_SYS_DCACHE_OFF
212 #define CONFIG_SYS_FSL_USDHC_NUM 3
217 #define CONFIG_VIDEO_IPUV3
218 #define CONFIG_CFB_CONSOLE
219 #define CONFIG_VGA_AS_SINGLE_DEVICE
220 #define CONFIG_SYS_CONSOLE_FG_COL 0xFF
221 #define CONFIG_SYS_CONSOLE_BG_COL 0x00
222 #define CONFIG_HIDE_LOGO_VERSION
223 #define CONFIG_IMX_HDMI
224 #define CONFIG_IMX_VIDEO_SKIP
225 #define CONFIG_CMD_BMP
228 #define CONFIG_PWM_IMX
229 #define CONFIG_IMX6_PWM_PER_CLK 66000000
232 #define CONFIG_PCI_PNP
233 #define CONFIG_PCI_SCAN_SHOW
234 #define CONFIG_PCIE_IMX
235 #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12)
236 #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(1, 5)
238 #define CONFIG_RTC_RX8010SJ
239 #define CONFIG_SYS_RTC_BUS_NUM 2
240 #define CONFIG_SYS_I2C_RTC_ADDR 0x32
243 #define CONFIG_SYS_I2C
244 #define CONFIG_SYS_I2C_MXC
245 #define CONFIG_SYS_I2C_SPEED 100000
246 #define CONFIG_SYS_I2C_MXC_I2C1
247 #define CONFIG_SYS_I2C_MXC_I2C2
248 #define CONFIG_SYS_I2C_MXC_I2C3
250 #define CONFIG_SYS_NUM_I2C_BUSES 11
251 #define CONFIG_SYS_I2C_MAX_HOPS 1
252 #define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \
253 {1, {I2C_NULL_HOP} }, \
254 {2, {I2C_NULL_HOP} }, \
255 {0, {{I2C_MUX_PCA9547, 0x70, 0} } }, \
256 {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
257 {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
258 {0, {{I2C_MUX_PCA9547, 0x70, 3} } }, \
259 {0, {{I2C_MUX_PCA9547, 0x70, 4} } }, \
260 {0, {{I2C_MUX_PCA9547, 0x70, 5} } }, \
261 {0, {{I2C_MUX_PCA9547, 0x70, 6} } }, \
262 {0, {{I2C_MUX_PCA9547, 0x70, 7} } }, \
267 #endif /* __GE_BX50V3_CONFIG_H */