2 * (C) Copyright 2003-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Eric Schumann, Phytec Messatechnik GmbH
9 * Jon Smirl <jonsmirl@gmail.com>
12 * Eric Millbrandt, DEKA Research and Development Corporation
14 * See file CREDITS for list of people who contributed to this
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
36 #define CONFIG_BOARDINFO "galaxy5200"
39 * High Level Configuration Options
42 #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
43 #define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
44 #define CONFIG_SYS_MPC5XXX_CLKIN 33333333 /* ... running at 33.333333MHz */
45 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
46 #define BOOTFLAG_WARM 0x02 /* Software reboot */
49 * Valid values for CONFIG_SYS_TEXT_BASE are:
50 * 0xFFF00000 boot high (standard configuration)
52 * 0x00100000 boot from RAM (for testing only) does not work
54 #ifdef CONFIG_galaxy5200_LOWBOOT
55 #define CONFIG_SYS_TEXT_BASE 0xFE000000
58 #ifndef CONFIG_SYS_TEXT_BASE
59 #define CONFIG_SYS_TEXT_BASE 0xFFF00000 /* Standard: boot high */
63 * Serial console configuration
65 #define CONFIG_PSC_CONSOLE 4 /* console is on PSC4 -> */
66 /* define gps port conf. */
67 /* register later on to */
68 /* enable UART function! */
69 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
70 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
73 * Command line configuration.
75 #include <config_cmd_default.h>
77 #define CONFIG_CMD_DATE
78 #define CONFIG_CMD_DHCP
79 #define CONFIG_CMD_EEPROM
80 #define CONFIG_CMD_I2C
81 #define CONFIG_CMD_JFFS2
82 #define CONFIG_CMD_MII
83 #define CONFIG_CMD_NFS
84 #define CONFIG_CMD_SNTP
85 #define CONFIG_CMD_PING
86 #define CONFIG_CMD_ASKENV
87 #define CONFIG_CMD_USB
88 #define CONFIG_CMD_CACHE
89 #define CONFIG_CMD_FAT
91 #define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
93 #if (CONFIG_SYS_TEXT_BASE == 0xFE000000) /* Boot low */
94 #define CONFIG_SYS_LOWBOOT 1
96 /* RAMBOOT will be defined automatically in memory section */
98 #define MTDIDS_DEFAULT "nor0=physmap-flash.0"
99 #define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:256k(ubootl)," \
100 "1792k(kernel),13312k(jffs2),256k(uboot)ro,256k(oftree),-(space)"
105 #define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */
106 #define CONFIG_ZERO_BOOTDELAY_CHECK /* allow stopping of boot process */
107 /* even with bootdelay=0 */
108 #define CONFIG_BOOT_RETRY_TIME 120 /* Reset if no command is entered */
109 #define CONFIG_RESET_TO_RETRY
111 #define CONFIG_PREBOOT "echo;" \
112 "echo Welcome to U-Boot;"\
115 #define CONFIG_BOOTCOMMAND "go ff300004 0; go ff300004 2 2;" \
116 "bootm ff040000 ff900000 fffc0000"
117 #define CONFIG_BOOTARGS "console=ttyPSC0,115200"
118 #define CONFIG_EXTRA_ENV_SETTINGS "epson=yes\0"
121 * IPB Bus clocking configuration.
123 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
124 #define CONFIG_SYS_XLB_PIPELINING 1
129 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
130 #define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
131 #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
132 #define CONFIG_SYS_I2C_SLAVE 0x7F
133 #define CONFIG_SYS_I2C_INIT_MPC5XXX /* Reset devices on i2c bus */
136 * EEPROM CAT24WC32 configuration
138 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* 1010100x */
139 #define CONFIG_SYS_I2C_FACT_ADDR 0x52 /* EEPROM CAT24WC32 */
140 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
141 #define CONFIG_SYS_EEPROM_SIZE 4096
142 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
143 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 15
149 #define CONFIG_RTC_DS3231 1
150 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
153 * Flash configuration
156 #define CONFIG_SYS_FLASH_BASE 0xfe000000
158 * The flash size is autoconfigured, but arch/powerpc/cpu/mpc5xxx/cpu_init.c needs this
161 #define CONFIG_SYS_FLASH_SIZE 0x02000000
162 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
164 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
165 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
166 #define CONFIG_SYS_FLASH_EMPTY_INFO
167 #define CONFIG_SYS_MAX_FLASH_SECT 259 /* max num of sects on one chip */
168 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
169 /* (= chip selects) */
170 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
173 * Use hardware protection. This seems required, as the BDI uses hardware
174 * protection. Without this, U-Boot can't work with this sectors as its
175 * protection is software only by default.
177 #define CONFIG_SYS_FLASH_PROTECTION 1
180 * Environment settings
183 #define CONFIG_ENV_IS_IN_EEPROM 1
184 #define CONFIG_ENV_OFFSET 0x00 /* environment starts at the */
185 /* beginning of the EEPROM */
186 #define CONFIG_ENV_SIZE CONFIG_SYS_EEPROM_SIZE
188 #define CONFIG_ENV_OVERWRITE 1
191 * SDRAM configuration
194 #define SDRAM_MODE 0x018D0000
195 #define SDRAM_EMODE 0x40090000
196 #define SDRAM_CONTROL 0x71500F00
197 #define SDRAM_CONFIG1 0x73711930
198 #define SDRAM_CONFIG2 0x47770000
203 #define CONFIG_SYS_MBAR 0xF0000000 /* MBAR has to be switched by other */
204 /* bootloader or debugger config */
205 #define CONFIG_SYS_SDRAM_BASE 0x00000000
206 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
208 /* Use SRAM until RAM will be available */
209 #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
211 /* End of used area in SPRAM */
212 #define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
214 /* Size in bytes reserved for initial data */
215 #define CONFIG_SYS_GBL_DATA_SIZE 128
217 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
218 CONFIG_SYS_GBL_DATA_SIZE)
219 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
221 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
222 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
223 # define CONFIG_SYS_RAMBOOT 1
226 #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
227 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
228 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
230 /* Chip Select configuration for NAND flash */
231 #define CONFIG_SYS_CS1_START 0x20000000
232 #define CONFIG_SYS_CS1_SIZE 0x90000
233 #define CONFIG_SYS_CS1_CFG 0x00025b00
235 /* Chip Select configuration for Epson S1D13513 */
236 #define CONFIG_SYS_CS3_START 0x10000000
237 #define CONFIG_SYS_CS3_SIZE 0x400000
238 #define CONFIG_SYS_CS3_CFG 0xffff3d10
241 * Ethernet configuration
243 #define CONFIG_MPC5xxx_FEC 1
244 #define CONFIG_MPC5xxx_FEC_MII100
245 #define CONFIG_PHY_ADDR 0x01
246 #define CONFIG_NO_AUTOLOAD 1
251 * GPS port configuration
255 * PSC1_0 -> AC97 SDATA out
256 * PSC1_1 -> AC97 SDTA in
257 * PSC1_2 -> AC97 SYNC out
258 * PSC1_3 -> AC97 bitclock out
259 * PSC1_4 -> AC97 reset out
275 * PSC3_0 -> USB_OE OE out
276 * PSC3_1 -> USB_TXN Tx- out
277 * PSC3_2 -> USB_TXP Tx+ out
279 * PSC3_4 -> USB_RXP Rx+ in
280 * PSC3_5 -> USB_RXN Rx- in
281 * PSC3_6 -> USB_PWR PortPower out
282 * PSC3_7 -> USB_SPEED speed out
283 * PSC3_8 -> USB_SUSPEND suspend
284 * PSC3_9 -> USB_OVRCURNT overcurrent in
290 * USB differential mode
296 * Ethernet 100Mbit with MD
307 * ETH_10 -> ETH Collision
313 * ETH_16 -> ETH Rxerr
324 * IrDA/USB 48MHz clock generated internally
327 * ATA chip selects on csb_4/5
328 * CSB_4 -> ATA_CS0 out
329 * CSB_5 -> ATA_CS1 out
332 * PSC3_4 is used as CS6
335 * PSC3_5 is used as CS7
341 * gpio_wkup_7 is GPIO
344 * gpio_wkup_6 is GPIO
347 #define CONFIG_SYS_GPS_PORT_CONFIG 0x0d75a162
350 * Miscellaneous configurable options
352 #define CONFIG_SYS_LONGHELP /* undef to save memory */
353 #define CONFIG_SYS_PROMPT "uboot> " /* Monitor Command Prompt */
355 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
357 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
358 #if defined(CONFIG_CMD_KGDB)
359 #define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
362 #if defined(CONFIG_CMD_KGDB)
363 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
365 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
367 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
368 /* Print Buffer Size */
369 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */
370 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
372 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
373 #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
375 #define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
376 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
378 #define CONFIG_DISPLAY_BOARDINFO 1
380 #define CONFIG_SYS_HUSH_PARSER 1
381 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
383 #define CONFIG_CRC32_VERIFY 1
385 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
387 CONFIG_BOOTP_DNS2 | \
388 CONFIG_BOOTP_SEND_HOSTNAME )
390 #define CONFIG_VERSION_VARIABLE 1
393 * Various low-level settings
395 #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
396 #define CONFIG_SYS_HID0_FINAL HID0_ICE
398 /* no burst access on the LPB */
399 #define CONFIG_SYS_CS_BURST 0x00000000
400 /* one deadcycle for the 33MHz statemachine */
401 #define CONFIG_SYS_CS_DEADCYCLE 0x33333331
403 #define CONFIG_SYS_BOOTCS_CFG 0x0002d900
404 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
405 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
407 #define CONFIG_SYS_RESET_ADDRESS 0xff000000
412 #define CONFIG_USB_CLOCK 0x0001bbbb
414 #define CONFIG_PSC3_USB
415 #define CONFIG_USB_CONFIG 0x00000100
416 #define CONFIG_USB_OHCI
417 #define CONFIG_USB_STORAGE
420 * IDE/ATA stuff Supports IDE harddisk
422 #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
423 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
424 #undef CONFIG_IDE_LED /* LED for ide not supported */
426 #define CONFIG_IDE_RESET 1 /* reset for ide supported */
427 #define CONFIG_IDE_PREINIT
428 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
429 #define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
430 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
431 #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
432 /* Offset for data I/O */
433 #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
434 /* Offset for normal register accesses */
435 #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
436 /* Offset for alternate registers */
437 #define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
438 /* Interval between registers */
439 #define CONFIG_SYS_ATA_STRIDE 4
440 #define CONFIG_ATAPI 1
442 /* we enable IDE and FAT support, so we also need partition support */
443 #define CONFIG_DOS_PARTITION 1
446 * Open Firmware flat tree
448 #define CONFIG_OF_LIBFDT 1
449 #define CONFIG_OF_BOARD_SETUP 1
451 #define OF_CPU "PowerPC,5200@0"
452 #define OF_TBCLK CONFIG_SYS_MPC5XXX_CLKIN
453 #define OF_SOC "soc5200@f0000000"
454 #define OF_STDOUT_PATH "/soc5200@f0000000/serial@2600"
456 #endif /* __CONFIG_H */