2 * Copyright (C) 2013 Samsung Electronics
4 * Configuration settings for the SAMSUNG EXYNOS5 board.
6 * SPDX-License-Identifier: GPL-2.0+
9 #ifndef __CONFIG_EXYNOS5_COMMON_H
10 #define __CONFIG_EXYNOS5_COMMON_H
12 #define CONFIG_EXYNOS5 /* Exynos5 Family */
14 #include "exynos-common.h"
16 #define CONFIG_SYS_CACHELINE_SIZE 64
17 #define CONFIG_ARCH_EARLY_INIT_R
18 #define CONFIG_EXYNOS_SPL
20 /* Allow tracing to be enabled */
22 #define CONFIG_CMD_TRACE
23 #define CONFIG_TRACE_BUFFER_SIZE (16 << 20)
24 #define CONFIG_TRACE_EARLY_SIZE (8 << 20)
25 #define CONFIG_TRACE_EARLY
26 #define CONFIG_TRACE_EARLY_ADDR 0x50000000
29 /* Enable ACE acceleration for SHA1 and SHA256 */
30 #define CONFIG_EXYNOS_ACE_SHA
31 #define CONFIG_SHA_HW_ACCEL
33 /* Power Down Modes */
34 #define S5P_CHECK_SLEEP 0x00000BAD
35 #define S5P_CHECK_DIDLE 0xBAD00000
36 #define S5P_CHECK_LPA 0xABAD0000
38 /* Offset for inform registers */
39 #define INFORM0_OFFSET 0x800
40 #define INFORM1_OFFSET 0x804
41 #define INFORM2_OFFSET 0x808
42 #define INFORM3_OFFSET 0x80c
44 /* select serial console configuration */
45 #define CONFIG_BAUDRATE 115200
46 #define EXYNOS5_DEFAULT_UART_OFFSET 0x010000
47 #define CONFIG_SILENT_CONSOLE
48 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
49 #define CONFIG_CONSOLE_MUX
51 #define EXYNOS_DEVICE_SETTINGS \
56 #define CONFIG_EXTRA_ENV_SETTINGS \
57 EXYNOS_DEVICE_SETTINGS
59 #define CONFIG_CMD_PING
60 #define CONFIG_CMD_ELF
61 #define CONFIG_CMD_NET
62 #define CONFIG_CMD_HASH
64 /* Thermal Management Unit */
65 #define CONFIG_EXYNOS_TMU
66 #define CONFIG_CMD_DTT
67 #define CONFIG_TMU_CMD_DTT
71 #define CONFIG_CMD_TPM
72 #define CONFIG_TPM_TIS_I2C
73 #define CONFIG_TPM_TIS_I2C_BUS_NUMBER 3
74 #define CONFIG_TPM_TIS_I2C_SLAVE_ADDR 0x20
77 #define COPY_BL2_FNPTR_ADDR 0x02020030
78 #define CONFIG_SUPPORT_EMMC_BOOT
80 #define CONFIG_SPL_LIBCOMMON_SUPPORT
81 #define CONFIG_SPL_GPIO_SUPPORT
83 /* specific .lds file */
84 #define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds"
86 /* Miscellaneous configurable options */
87 #define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
88 /* Boot Argument Buffer Size */
89 /* memtest works on */
90 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
91 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
92 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
96 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
97 #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
98 #define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
99 #define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
100 #define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
101 #define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
102 #define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
103 #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
104 #define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
105 #define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
106 #define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
107 #define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
108 #define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
109 #define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
110 #define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
111 #define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
113 #define CONFIG_SYS_MONITOR_BASE 0x00000000
115 #define CONFIG_SYS_MMC_ENV_DEV 0
117 #define CONFIG_SECURE_BL1_ONLY
119 /* Secure FW size configuration */
120 #ifdef CONFIG_SECURE_BL1_ONLY
121 #define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */
123 #define CONFIG_SEC_FW_SIZE 0
126 /* Configuration of BL1, BL2, ENV Blocks on mmc */
127 #define CONFIG_RES_BLOCK_SIZE (512)
128 #define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
129 #define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */
130 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
132 #define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
133 #define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
135 /* Store environment at the end of a 4 MB SPI flash */
136 #define FLASH_SIZE (0x4 << 20)
137 #define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE)
139 /* U-boot copy size from boot Media to DRAM.*/
140 #define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512)
141 #define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512)
143 #define CONFIG_SPI_BOOTING
144 #define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058
145 #define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
148 #define CONFIG_SYS_I2C_INIT_BOARD
149 #define CONFIG_SYS_I2C
150 #define CONFIG_CMD_I2C
151 #define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* 100 Kbps */
152 #define CONFIG_SYS_I2C_S3C24X0
153 #define CONFIG_I2C_MULTI_BUS
154 #define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x0
155 #define CONFIG_I2C_EDID
158 #define CONFIG_ENV_IS_IN_SPI_FLASH
159 #define CONFIG_SPI_FLASH
160 #define CONFIG_ENV_SPI_BASE 0x12D30000
162 #ifdef CONFIG_SPI_FLASH
163 #define CONFIG_EXYNOS_SPI
164 #define CONFIG_CMD_SF
165 #define CONFIG_CMD_SPI
166 #define CONFIG_SPI_FLASH_WINBOND
167 #define CONFIG_SPI_FLASH_GIGADEVICE
168 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
169 #define CONFIG_SF_DEFAULT_SPEED 50000000
170 #define EXYNOS5_SPI_NUM_CONTROLLERS 5
171 #define CONFIG_OF_SPI
174 #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
175 #define CONFIG_ENV_SPI_MODE SPI_MODE_0
176 #define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
177 #define CONFIG_ENV_SPI_BUS 1
178 #define CONFIG_ENV_SPI_MAX_HZ 50000000
181 /* Ethernet Controllor Driver */
182 #ifdef CONFIG_CMD_NET
183 #define CONFIG_SMC911X
184 #define CONFIG_SMC911X_BASE 0x5000000
185 #define CONFIG_SMC911X_16_BIT
186 #define CONFIG_ENV_SROM_BANK 1
187 #endif /*CONFIG_CMD_NET*/
189 /* Enable PXE Support */
190 #ifdef CONFIG_CMD_NET
191 #define CONFIG_CMD_PXE
196 #define CONFIG_CMD_HASH
197 #define CONFIG_HASH_VERIFY
199 #define CONFIG_SHA256
201 /* Enable Time Command */
202 #define CONFIG_CMD_TIME
204 #define CONFIG_CMD_BOOTZ
206 #define CONFIG_CMD_GPIO
209 #define CONFIG_USB_BOOTING
210 #define EXYNOS_COPY_USB_FNPTR_ADDR 0x02020070
211 #define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002
212 #define EXYNOS_IRAM_SECONDARY_BASE 0x02020018
214 /* Enable FIT support and comparison */
216 #define CONFIG_FIT_BEST_MATCH
218 #endif /* __CONFIG_EXYNOS5_COMMON_H */